A semiconductor device includes a cell portion and a peripheral portion. The cell portion has a semiconductor element including a drift layer, a first impurity region, a second impurity region, trench-gate structures, a high-concentration layer, an interlayer insulating film, a first electrode and a second electrode. The interlayer insulating film is located on the trench-gate structures, the first impurity region and the second impurity region, and has a first contact hole communicating with the first impurity region and the second impurity region. The peripheral portion has a section facing the cell portion in one direction, and the interlayer insulating film further has a second contact hole at the section of the peripheral portion. The second contact hole exposes the first impurity region, and the first electrode is electrically connected to the first impurity region through the second contact hole in the peripheral portion.

A semiconductor device includes a source region. A drain region has a first conductivity type and a second dopant concentration spaced apart from the source region. A first drift region is located between the source region and the drain region and has the first conductivity type and a first dopant concentration that is lower than the second dopant concentration of the drain region. An oxide structure includes a first portion on or over the first drift region and a tapered portion between the first portion and the drain region. A substrate surface extension is between the tapered portion and the drain region. A buffer region has the first conductivity type between the first drift region and the drain region and under the tapered portion of the oxide structure. The buffer region has a third dopant concentration between the second dopant concentration and the first dopant concentration.

An IC device includes first and second CMOS structures positioned in n-type doped regions of a substrate, the first CMOS structure including a common gate terminal, first NMOS body and source contacts, and first PMOS body and source contacts, the second CMOS structure including a common drain terminal, second NMOS body and source contacts, and second PMOS body and source contacts. The IC device includes a first electrical connection from the common drain terminal to the common gate terminal, a clamp device including a diode, a second electrical connection from a cathode of the diode to the first PMOS body and source contacts, and a third electrical connection from an anode of the of the diode to the first NMOS body and source contacts, and entireties of each of the second and third electrical connections are positioned between the substrate and a third metal layer of the IC device.

A method includes: forming a barrier layer in a substrate; depositing a first dielectric layer over the substrate; forming a patterned mask layer over the first dielectric layer; patterning the first dielectric layer into a first sublayer of a gate dielectric layer; converting at least part of the patterned mask layer into a second sublayer of the gate dielectric layer; depositing a second dielectric layer adjacent to the first and second sublayers to serve as a third sublayer of the gate dielectric layer; and depositing a gate electrode over the gate dielectric layer.

A silicon carbide semiconductor device includes a silicon carbide substrate having first and second main surfaces and including an electric field relaxation region and a connection region. A gate trench provided in the first main surface is defined by side surfaces and a bottom surface. The electric field relaxation region is a second conductivity type and provided between the bottom surface and the second main surface, and the connection region is the second conductivity type and electrically connects a contact region including first and second regions to the electric field relaxation region. In plan view, the gate trench and the electric field relaxation region are located on a virtual straight line. The first region is in contact with the connection region on the virtual straight line, and the second region is provided on a position where the source region is sandwiched between the gate trench and the second region.

A silicon carbide semiconductor device includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface. The silicon carbide substrate includes a drift region being a first-conductivity type, a body region being a second-conductivity type and provided on the drift region, a source region being the first-conductivity type and provided on the body region such that the source region is separated from the drift region, a contact region being the second-conductivity type and provided on the body region. Gate trenches are provided in the first main surface, and extend in a first direction parallel to the first main surface. The contact region is in contact with a first gate trench from both sides in a second direction orthogonal to the first direction and spaced apart from a second gate trench adjacent to the first gate trench in the second direction.

A semiconductor structure includes: a semiconductor substrate; a gate dielectric layer over the semiconductor substrate; and a gate electrode over the gate dielectric layer. The gate dielectric layer includes a first portion and a second portion thinner than the first portion, wherein the gate electrode is over the first portion and the second portion, and the first portion includes a third portion including nitrogen and enclosed by the first portion.