A semiconductor device structure includes a hybrid substrate having a semiconductor-on-insulator (SOI) region that includes an active semiconductor layer, a substrate material and a buried insulating material interposed between the active semiconductor layer and the substrate material, and a bulk semiconductor region that includes the substrate material. An insulating structure is positioned in the hybrid substrate, wherein the insulating structure separates the bulk region from the SOI region, and a gate electrode is positioned above the substrate material in the bulk region, wherein the insulating structure is in contact with two opposing sidewalls of the gate electrode.

A memory cell disposed on a substrate has a first gate structure and a second gate structure. The memory cell includes a first heavily doped region adjacent to an outer side of the first gate structure. Further, a first lightly doped drain (LDD) region with a first type dopant is between the first heavily doped region and the outer side of the first gate structure. A pocket doped region with a second type dopant is overlapping with the first LDD region. The second type dopant is opposite to the first type dopant in conductive type. A second heavily doped region is adjacent to an outer side of the second gate structure, opposite to the first heavily doped region. A second LDD region with the first type dopant is disposed between the first gate structure and the second gate structure.

Metal floating gate electrodes can be formed for a three-dimensional memory device by forming a memory opening having lateral recesses at levels of spacer material layers between insulating layers, depositing a continuous metal layer, and inducing diffusion and agglomeration of the metal into the lateral recesses to form discrete metal portions employing an anneal process. The metallic material can migrate and form the discrete metal portions due to surface tension, which operates to minimize the surface area of the metallic material. Optionally, two or more continuous metal layers can be employed to form discrete metal portions including at least two metals. Optionally, a selective metal deposition process can be performed to deposit additional metal portions including a different metallic material on the discrete metal portions. The metal floating gate electrodes can be formed without employing an etch process. A tunneling dielectric layer and a semiconductor channel can be subsequently formed.

A method for producing a semiconductor device includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film; a second step of forming a pillar-shaped semiconductor layer and a first dummy gate; a third step of forming a second dummy gate; a fourth step of forming a fifth insulating film and a sixth insulating film; a fifth step of depositing a first interlayer insulating film, removing the second dummy gate and the first dummy gate, forming a gate insulating film, depositing metal, and performing etch back to form a gate electrode and a gate line; a seventh step of forming a seventh insulating film; and an eighth step of forming insulating film sidewalls, forming a first epitaxially grown layer on the fin-shaped semiconductor layer, and forming a second epitaxially grown layer on the pillar-shaped semiconductor layer.

A method for forming a semiconductor device structure is provided. The method includes forming a mask layer over a substrate. The method includes forming a first isolation structure and a second isolation structure passing through the mask layer and penetrating into the substrate. The method includes thinning the mask layer to expose a first portion of the first isolation structure and a second portion of the second isolation structure. The method includes partially removing the first portion, the second portion, the third portion, and the fourth portion. The method includes removing the thinned mask layer. The method includes forming a first gate over the substrate and between the first isolation structure and the second isolation structure. The method includes forming a dielectric layer over the first gate. The method includes forming a second gate over the dielectric layer and above the first gate.

A memory device including a silicon semiconductor substrate, spaced apart source and drain regions formed in the substrate with a channel region there between, and a conductive floating gate disposed over a first portion of the channel region and a first portion of the source region. An erase gate includes a first portion that is laterally adjacent to the floating gate and over the source region, and a second portion that extends up and over the floating gate. A conductive word line gate is disposed over a second portion of the channel region. The word line gate is disposed laterally adjacent to the floating gate and includes no portion disposed over the floating gate. The thickness of insulation separating the word line gate from the second portion of the channel region is less than that of insulation separating the floating gate from the erase gate.

Provided is a method of forming a decoupling capacitor device and the device thereof. The decoupling capacitor device includes a first dielectric layer portion that is deposited in a deposition process that also deposits a second dielectric layer portion for a non-volatile memory cell. Both portions are patterned using a single mask. A system-on-chip (SOC) device is also provided, the SOC include an RRAM cell and a decoupling capacitor situated in a single inter-metal dielectric layer. Also a method for forming a process-compatible decoupling capacitor is provided. The method includes patterning a top electrode layer, an insulating layer, and a bottom electrode layer to form a non-volatile memory element and a decoupling capacitor.

A method of fabricating a tunnel oxide layer for a semiconductor memory device, the method comprising: fabricating on a substrate a first oxide layer by an in-situ-steam-generation process; and fabricating at least one further oxide layer by a furnace oxidation process, wherein during fabrication of the at least one further oxide layer, reactive gases penetrate the first oxide layer and react with the silicon substrate to form at least a first portion of the at least one further oxide layer beneath the first oxide layer.

Various embodiments include apparatuses and methods of forming the same. One such apparatus can include a first dielectric material and a second dielectric material, and a conductive material between the first dielectric material and the second dielectric material. A charge storage element, such as a floating gate or charge trap, is between the first dielectric material and the second dielectric material and adjacent to the conductive material. The charge storage element has a first surface and a second surface. The first and second surfaces are substantially separated from. the first dielectric material and the second dielectric material, respectively, by a first air gap and a second air gap. Additional apparatuses and methods are disclosed.

A semiconductor device includes a substrate, a tunnel insulation pattern on the substrate, a charge storage pattern on the tunnel insulation pattern, a dielectric pattern having a width smaller than a width of the charge storage pattern on the charge storage pattern, a control gate having a width greater than the width of the dielectric pattern on the dielectric pattern, and a metal-containing gate on the control gate.