A ranging apparatus includes a first array with first light sensitive detectors configured to receive light which has been reflected by an object and generate an output. A second array, spaced apart from the first array by a spacing distance, is further included, the second array having second light sensitive detectors. The second array is configurable to either receive light which has been reflected by the object or to be a reference array and generate an output. A processor operates to determine a distance to the object in response to the outputs from the first and the second arrays.

A sensing device includes an array of sensing elements. Each sensing element includes a photodiode, including a p-n junction, and a local biasing circuit, coupled to reverse-bias the p-n junction at a bias voltage greater than a breakdown voltage of the p-n junction by a margin sufficient so that a single photon incident on the p-n junction triggers an avalanche pulse output from the sensing element. A bias control circuit is coupled to set the bias voltage in different ones of the sensing elements to different, respective values that are greater than the breakdown voltage.

A ranging apparatus includes an array of light sensitive detectors configured to receive light from a light source which has been reflected by an object. The array includes a number of different zones. Readout circuitry including at least one read out channel is configured to read data output from each of the zones. A processor operates to process the data output to determine position information associated with the object.

To provide an imaging device capable of high-speed reading. The imaging device includes a photodiode, a first transistor, a second transistor, a third transistor, and a fourth transistor. The back gate electrode of the first transistor is electrically connected to a wiring that can supply a potential higher than a source potential of the first transistor and a potential lower than the source potential of the first transistor. The back gate electrode of the second transistor is electrically connected to a wiring that can supply a potential higher than a source potential of the second transistor. The back gate electrode of the third transistor is electrically connected to a wiring that can supply a potential higher than a source potential of the third transistor and a potential lower than the source potential of the third transistor.

A p.sup. type semiconductor substrate 20 has a first principal surface 20a and a second principal surface 20b opposed to each other and includes a photosensitive region 21. The photosensitive region 21 is composed of an n.sup.+ type impurity region 23, a p.sup.+ type impurity region 25, and a region to be depleted with application of a bias voltage in the p.sup. type semiconductor substrate 20. An irregular asperity 10 is formed in the second principal surface 20b of the p.sup. type semiconductor substrate 20. An accumulation layer 37 is formed on the second principal surface 20b side of the p.sup. type semiconductor substrate 20 and a region in the accumulation layer 37 opposed to the photosensitive region 21 is optically exposed.

A photodetector according to an embodiment includes; at least one photodiode including: a first electrode; an n-type semiconductor layer disposed on the first electrode; a first p-type semiconductor layer disposed above the n-type semiconductor layer, the first p-type semiconductor layer including a first surface region and a second surface region; a second p-type semiconductor layer disposed in the first surface region of the first p-type semiconductor layer, the second p-type semiconductor layer having a higher p-type impurity concentration than the first p-type semiconductor layer; and a second electrode disposed on the second surface region of the first p-type semiconductor layer and on the second p-type semiconductor layer.

A circuit is provided. The circuit includes a single-photon avalanche diode. The circuit further includes a delay element comprising a first regulator and a second regulator, each of which is independently selectable based on a selection signal applied to a selection terminal of the delay element. The delay element is configured to receive, at an inverting section, an event signal indicative of an avalanche event in the single-photon avalanche diode. Furthermore, the delay element is configurable in one of two distinct delay resolution regimes, each corresponding to only one edge of the event signal being actively delayed by the delay element when one of the first regulator and the second regulator is enabled and the other one of the first regulator and the second regulator is turned off.

Photoelectric conversion device incudes first region of first conductivity type arranged in semiconductor layer having first second surfaces, second region of second conductivity type arranged between the second surface and the first region and forming avalanche photodiode, separation region of the second conductivity type arranged between the first and second surfaces to surround the second region, contact region of the second conductivity type contacted to the separation region, first contact plug connected to the first region, and second contact plug connected to the contact region. The second region has shape of rectangle, and the second contact plug is arranged in diagonal direction of the rectangle. Distance between center of the first contact plug and center of the second contact plug is larger than distance between center of the second region and the center of the second contact plug.

Embodiments of the disclosure provide a structure with a guard ring between the terminals of a single photon avalanche diode photodetector (SPAD), and related methods. A structure according to the disclosure includes a SPAD with an anode within a doped well and a cathode within the doped well. A guard ring includes a semiconductor material within the doped well. The semiconductor material and the doped well have opposite doping polarities.

A solid-state image sensor including a photoelectric conversion region partitioned by trenches, a first semiconductor region surrounding the photoelectric conversion region, a first contact in contact with the first semiconductor region at a bottom portion of the trench, a first electrode in contact with the first contact in the first trench, a second semiconductor region in contact with the first semiconductor region having the same conductive type as the first semiconductor region, a third semiconductor region in contact with the second semiconductor region, between the second semiconductor region and a first surface, and having a second conductive type, a second contact on the first surface in contact with the third semiconductor region, and a second electrode in contact with the second contact, and a second surface at which the first contact and the first electrode are in contact with each other is inclined with respect to the first surface.