A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.

A semiconductor device including a transistor section and a diode section, the semiconductor device having: a temperature sensing section; a neighboring transistor section adjacent to the temperature sensing section; a neighboring diode section adjacent to the temperature sensing section; and a first non-neighboring diode section that is not adjacent to the temperature sensing section, wherein the first non-neighboring diode section has a pattern different from the pattern of the neighboring diode section in the top view is provided.

Provided is a semiconductor device having transistor and diode sections. The semiconductor device comprises: a gate metal layer provided above the upper surface of a semiconductor substrate; an emitter electrode provided above the upper surface of the semiconductor substrate; a first conductivity-type emitter region provided on the semiconductor substrate upper surface side in the transistor section; a gate trench section, which is provided on the semiconductor substrate upper surface side in the transistor section, is electrically connected to the gate metal layer, and is in contact with the emitter region; an emitter trench section, which is provided on the semiconductor substrate upper surface side in the diode section, and is electrically connected to the emitter electrode; and a dummy trench section, which is provided on the semiconductor substrate upper surface side, is electrically connected to the gate metal layer, and is not in contact with the emitter region.

A method of manufacturing a radio frequency bipolar transistor includes fabricating a structure including a substrate having a main surface, a collector formed in the substrate, a monocrystalline base and a cavity. The collector faces the monocrystalline base in a first direction perpendicular to the main surface and the monocrystalline base faces the cavity in the first direction. A spacer layer is formed in the cavity and the spacer layer is contacting the monocrystalline base and extending in the first direction. An emitter is formed by selective epitaxial growing doped semiconductor material from a first region of the monocrystalline base wherein during the selective epitaxial growing a first sticking coefficient on the spacer layer is zero or a factor 1/10 or less of a second sticking coefficient on the monocrystalline base.

A semiconductor chip includes a semiconductor substrate, a plurality of first wirings extending in a first direction parallel to the upper surface of the semiconductor substrate and disposed entirely above the upper surface of the semiconductor substrate, a second wiring disposed between two of the first wirings that are adjacent to each other and entirely below the upper surface of the semiconductor substrate such that an upper surface of the second wiring is below a lower surface of the two first wirings, and a first insulating film provided on the second wiring and spaced apart from the two first wirings in a second direction that is perpendicular to the first direction, the first insulating film having an upper surface that is above the lower surface of the two first wirings.

A photodetector including a high electron mobility transistor (HEMT) device or an indium phosphide (InP)-based heterojunction bipolar transistor (HBT) device including a collector layer, a base layer formed on the collector layer and an emitter layer formed on the base layer. The photodetector also includes a nanowire array electrically coupled to the HEMT device or the base layer of the HBT device, and may include a first sub-array positioned on one side of the emitter layer and second sub-array positioned on an opposite side of the emitter layer. The nanowire array includes a plurality of spaced apart and conical-shaped InP nanowires encased in a transparent medium, and are operable to absorb light over a wavelength band of 400-925 nm and convert the light to an electrical signal that is received by the HEMT or HBT device.

A semiconductor device includes a semiconductor body having first and second surfaces opposite to each other. The semiconductor body includes a first well region having a first conductivity type, second and third well regions spaced apart from each other in a first direction with the first well region interposed therebetween and having a second conductivity type, first doped regions spaced apart from each other in a second direction intersecting the first direction in the first well region, a second doped region, which is adjacent to the second well region and has the second conductivity type, and a third doped region, which is adjacent to the third well region and has the second conductivity type. The second surface of the semiconductor body includes bottom surfaces of the first to third well regions, the plurality of first doped regions, the second doped region, and the third doped region.

A semiconductor device includes, within an outer peripheral region: an outer peripheral p-type layer; an outer peripheral n-type layer positioned on an outer peripheral side relative to the outer peripheral p-type layer with a space from the outer peripheral p-type layer; a high breakdown voltage p-type layer arranged to include a portion of an upper surface of a semiconductor substrate located between the outer peripheral p-type layer and the outer peripheral n-type layer; a drift n-type layer extending up to the upper surface between the high breakdown voltage p-type layer and the outer peripheral n-type layer; a protective electrode disposed above the high breakdown voltage p-type layer via an interlayer insulating film and electrically connected to an upper electrode; and a semi-insulating film covering the upper surface between the protective electrode and the outer peripheral n-type layer and having a resistivity of 110.sup.8 .Math.cm to 110.sup.14 .Math.cm at 25 C.