Apparatus and methods for electrical overstress (EOS) protection circuits are provided herein. In certain configurations, an EOS protection circuit includes an overstress sensing circuit electrically connected between a pad and a first supply node, an impedance element electrically connected between the pad and a signal node, a controllable clamp electrically connected between the signal node and the first supply node and selectively activatable by the overstress sensing circuit, and an overshoot limiting circuit electrically connected between the signal node and a second supply node. The overstress sensing circuit activates the controllable clamp when an EOS event is detected at the pad. Thus, the EOS protection circuit is arranged to divert charge associated with the EOS event away from the signal node to provide EOS protection.

Circuit configurations and related methods are provided that may be implemented using insulated-gate bipolar transistor (IGBT) device circuitry to protect at risk circuitry (e.g., such as high voltage output buffer circuitry or any other circuitry subject to undesirable ESD events) from damage due to ESD events that may occur during system assembly. The magnitude of the trigger voltage V.sub.T1 threshold for an IGBT ESD protection device may be dynamically controlled between at least two different values so that trigger voltage V.sub.T1 threshold for an IGBT ESD protection device may be selectively reduced when needed to better enable ESD operation.

Interconnects (34) include an inside interconnect section (40) and an outside interconnect section (41). The inside interconnect section (40) includes a first interconnect layer (42), a second interconnect layer (43), and a connection section (44) that connects the first interconnect layer (42) and the second interconnect layer (43). The outside interconnect section (41) includes a third interconnect layer (45). Of a plurality of interconnects (34), in one interconnect (X) of neighboring interconnects the second interconnect layer (43) and the third interconnect layer (45) are connected, and in another of the neighboring interconnects (Y), the first interconnect layer (42) and the third interconnect layer (45) are connected.

A multi-gate Schottky depletion-mode field effect transistor (FET), at least one diode and two resistors comprise a compact electrostatic discharge (ESD) protection structure. This ESD protection structure can be laid out in a smaller area than typical multiple diode ESD devices. The multi-gate FET may comprise various types of high-electron-mobility transistor (HEMT) devices, e.g., (pseudomorphic) pHEMT, (metamorphic) mHEMT, induced HEMT. The multiple gates of the Schottky field effect device are used to form an ESD trigger and charge draining paths for protection of circuits following the ESD protection device. Both single and dual polarity ESD protection devices may be provided on an integrated circuit die for protection of input-output circuits thereof.

The short-circuit protection circuit for a Gate Driver on Array (GOA) liquid crystal panel contains a power module, a first booster module, a feedback module, and a second booster module series-connected in the this order. A control module is electrically connected to the first booster, feedback, and second booster modules. The power module provides a power voltage. The control module provides a pulse width modulation (PWM) signal so as to control the first and second booster modules to transform the power voltage into driving voltage. The feedback module extracts a feedback current from a current flowing from the first to the second booster module and provides a feedback signal to the control module. When the feedback current exceeds a current threshold, the control module cuts off the PWM signal output so as to achieve short-circuit protection. A liquid crystal panel incorporating the above short-circuit protection circuit is also provided.

A film-type semiconductor package includes a semiconductor integrated circuit and a dummy metal pattern. The semiconductor integrated circuit is formed on a film and includes an electrostatic discharge (ESD) protection circuit. The dummy metal pattern is formed on the film and is electrically connected to the ESD protection circuit through a first wiring formed on the film.

An electrostatic discharge (ESD) device for an integrated circuit includes a substrate having a longitudinally extending fin dispose thereon. A first n-type FinFET (NFET) is disposed within the fin. The NFET includes an n-type source, an n-type drain and a p-well disposed within the substrate under the source and drain. A p-type FinFET (PFET) is disposed within the fin. The PFET includes a p-type source/drain region and an n-well disposed within the substrate under the source/drain region. The n-well and p-well are located proximate enough to each other to form an np junction therebetween. The p-type source/drain region of the PFET and the n-type drain of the NFET are electrically connected to a common input node.

The present disclosure relates to an array substrate, a display panel and a display device. The array substrate includes GND wirings and GOA areas. The GND wirings are configured at outer sides of the GOA areas, and the GOA area includes a variety of GOA signal lines and N-th stage GOA circuits electrically connected by the GOA signal lines. A first ESD protection circuit is configured in a middle area between the 1-th stage GOA circuit and the N-th stage GOA circuit to discharge abnormal electrical charges of the GOA signal lines within the middle area. With such configuration, better ESD protection capability is provided between the GOA signal lines.

An integrated circuit (IC) structure is provided. The IC structure comprises a deep n-well (DWN), a first circuit, a second circuit, a first power line and a second power line. The first circuit is in the DWN. The second circuit is outside the DWN and electrically connected with the first circuit. The first power line is configured to provide the first circuit with power. The second power line is configured to provide the second circuit with power. The second power line is electrically connected with the first power line. The first power line and the second power line are in different conductive layers.

A device having an electrostatic discharge structure includes a bulk substrate having a first dopant conductivity, first wells formed adjacent to a surface of the bulk substrate, including a second dopant conductivity, and second wells formed adjacent to the surface of the bulk substrate within the first wells, including the first dopant conductivity. A supply bus is formed in one of the first wells outside the second well. A ground bus has a first portion formed in another first well outside the second well, and a second portion is formed inside the second well such that a charge input to the second wells is dissipated without accumulating in the bulk substrate.