A display panel includes: an electrostatic discharge (ESD) protection circuit area in a peripheral area surrounding a display area including pixels, the ESD protection circuit area including ESD protection circuits; a fan-out area in the peripheral area, including fan-out lines to receive data signals and a first pad to receive a first global signal; a common line area between the ESD protection circuit area and the fan-out area, including a first common line extending lengthwise in a pixel row direction; a first transmission line connecting lengthwise from the first pad to the first common line to transmit the first global signal to the first common line; and first global signal lines extending lengthwise in a pixel column direction from the first common line to the display area to concurrently transmit the first global signal to the pixels. The first transmission line is wider than the first global signal lines.

The present disclosure provides a light-emitting substrate, a backlight and a display device. The light-emitting substrate includes a light-emitting region and a peripheral region surrounding the light-emitting region. The peripheral region includes a first area, the first area is located between a first side of the light-emitting substrate and the light-emitting region, the light-emitting substrate further includes a first signal line, the first signal line includes at least one selected from a group consisting of a first portion and a second portion, the first portion of the first signal line extends along a first direction in the first area, the second portion of the first signal line extends into the light-emitting region, the first portion and the second portion of the first signal line are connected when the first signal line includes the first portion and the second portion.

An electrostatic protection circuit and a semiconductor device include: a first diode whose anode is connected to a signal terminal; a second diode whose cathode is connected to a cathode of the first diode and whose anode is connected to a GND terminal; and a depletion type MOS transistor connected in parallel with the first diode.

In certain aspects, a semiconductor device includes a device layer, a dummy pad, a dielectric structure between the device layer and the dummy pad and extending in a vertical direction, and an interconnect structure between the device layer and the dielectric structure and extending in the vertical direction. The dielectric structure, the interconnect structure, and the dummy pad are overlaid.

A semiconductor device includes a first diode having a first cathode and a first anode, wherein the first cathode is floating. The semiconductor device includes a second diode having a second cathode and a second anode, wherein the first anode is coupled to the second anode with the second cathode connected to a first supply voltage. The semiconductor device includes a third diode having a third cathode and a third anode, wherein the third cathode is connected to the first anode at an input/output pin, with the third anode connected to a second supply voltage. The second anode is coupled to a circuit that is powered by the first supply voltage and the second supply voltage. The first diode has a first size and the second diode has a second size, and the first size is substantially greater than the second size.

An ESD guard ring structure includes numerous first fin structures, numerous second fin structures, numerous first polysilicon conductive lines, numerous second polysilicon conductive lines, numerous third polysilicon conductive lines and numerous single diffusion breaks. Each of the first fin structures includes at least one single diffusion break therein. Each of the single diffusion breaks overlaps one of the third polysilicon conductive lines.

A method of making a semiconductor device includes manufacturing an ESD cell over a substrate, wherein the ESD cell includes multiple diodes connected in parallel to each other. The method includes manufacturing a conductive pillar electrically connected to the ESD cell of the semiconductor device; manufacturing a through-silicon via (TSV) extending through the substrate, wherein the TSV extends through the substrate within a TSV zone having a TSV zone perimeter, and wherein a first end of the TSV is at a same side of the substrate as the ESD cell, and a second end of the TSV is at a different side of the substrate from the ESD cell. The method includes manufacturing an antenna extending parallel to the TSV at a same side of the substrate as the ESD cell; and manufacturing an antenna pad electrically connected to the TSV, the antenna, and the conductive pillar.

A semiconductor wafer, a benchmark device embedded on a semiconductor wafer, and a method of operating a benchmark device embedded on a semiconductor wafer are provided. The semiconductor wafer includes a benchmark device disposed within a scribe line of the semiconductor wafer. The benchmark device includes a transistor, a diode, and a disconnecting switch electrically connected to the transistor and the diode. The disconnecting switch is configured to form a conductive path between the transistor and the diode at a first stage, and to electrically isolate the transistor from the diode at a second stage.

An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: an internal circuit patterned in a device wafer and electrically coupled between a first node and a second node, an array of electrostatic discharge (ESD) circuits patterned in a carrier wafer, where the ESD circuits are electrically coupled between a first node and a second node and configured to protect the internal circuit from transient ESD events, and where the device wafer is bonded to the carrier wafer.

In an embodiment a silicon substrate includes integrated circuits located on a first surface, a second surface opposite to the first surface, a first via and an ESD protection element, wherein the ESD protection element is fully integrated into the silicon substrate, wherein the ESD protection element is spatially distant from the first via, wherein the ESD protection element is connected to the via by a first rewiring, and wherein the ESD protection element comprises a suppressor diode, a transistor or a thyristor.