An electrostatic discharge (ESD) device for an integrated circuit includes a substrate having a longitudinally extending fin dispose thereon. A first n-type FinFET (NFET) is disposed within the fin. The NFET includes an n-type source, an n-type drain and a p-well disposed within the substrate under the source and drain. A p-type FinFET (PFET) is disposed within the fin. The PFET includes a p-type source/drain region and an n-well disposed within the substrate under the source/drain region. The n-well and p-well are located proximate enough to each other to form an np junction therebetween. The p-type source/drain region of the PFET and the n-type drain of the NFET are electrically connected to a common input node.

The disclosed technology relates to electronics, and more particularly, to protection devices that protect circuits from transient electrical events such as electrical overstress/electrostatic discharge. A protection device includes a semiconductor substrate having formed therein at least two wells and a deep well underlying and contacting the at least two wells. The device additionally includes a first PN diode formed in one of the at least two wells and having a first heavily doped region of a first conductivity type and a first heavily doped region of a second conductivity type, and includes a second PN diode formed in one of the at least two wells and having a second heavily doped region of the first conductivity type and a second heavily doped region of the second conductivity type. The device additionally includes a first PN diode and the second PN diode are electrically shorted by an electrical shorting structure to form a first plurality of serially connected diodes having a threshold voltage. The device further includes a PNPN silicon-controlled rectifier (SCR) having a trigger voltage and comprising the first heavily doped region of the first conductivity type, the at least two wells, the deep well, and the second heavily doped region of the second conductivity type.

An electrostatic discharge (ESD) unit is described, including a first device, and a second device coupled to the first device in parallel. In an ESD event, the first device is turned on before the second device is turned on. The second device may be turned on by the turned-on first device to form an ESD path in the ESD event.

Capacitor cells are provided. A first PMOS transistor has a source connected to a power supply and a drain connected to a first node. A first NMOS transistor has a source connected to a ground and a drain connected to a second node. A second PMOS transistor has a source connected to the second node and a drain connected to the first node. A second NMOS transistor has a source connected to the ground and a drain connected to the first node. A first P+ doped region is shared by drains of the first and second PMOS transistors. A first gate metal is between the first P+ doped region and a second P+ doped region. A first N+ doped region is shared by sources of the first and second NMOS transistors. A second gate metal is between the first N+ doped region and a second N+ doped region.

The present disclosure concerns a switching device comprising a first phosphorus-doped silicon layer on top of and in contact with a second arsenic-doped silicon layer. The present disclosure also concerns a method of making a switching device that includes forming a phosphorus-doped silicon layer in an arsenic-doped silicon layer.

An electrostatic discharge (ESD), protection device is provided. In accordance with the present disclosure, an ESD protection device is provided that includes a series connection of a first unit having strong snapback and low series capacitance and a second high-voltage unit that displays a relatively high holding/trigger voltage to ensure latch up and improper triggering of the ESD protection device while at the same time providing high-voltage operation with low capacitive loading.

A protection device may include a semiconductor substrate and a thyristor-type device, formed within the semiconductor substrate, where the thyristor device extends from a first main surface of the semiconductor substrate to a second main surface of the semiconductor substrate. The protection device may include a first PN diode, formed within the semiconductor substrate; and a second PN diode, formed within the semiconductor substrate, wherein the thyristor-type device is arranged in electrical series between the first PN diode and the second PN diode.

The invention relates to an IC with an electrostatic discharge protection device. There is a buried insulant layer 50 nm or less in thickness and first and second bipolar transistors on the insulant layer, one being an npn transistor and the other a pnp transistor. The base of the first transistor is merged with the collector of the second transistor and the base of the second transistor is merged with the collector of the first transistor. The first and second bipolar transistors are configured to selectively conduct a discharge current between two electrodes of the protection device. There is a first semiconductor ground plane under the insulant layer, being electrically biased, extending until it is plumb with the base of the first bipolar transistor, exhibiting a first type of doping identical to that of the base of the first bipolar transistor with a doping density at least ten times greater.

An electronic device is formed by a sequence of at least two thyristors coupled in series in a same conduction direction. Each thyristor has a gate of a first conductivity type. The gates of the first conductivity type for the thyristors in the sequence are coupled together in order to form a single control gate.

An electrostatic discharge protection clamp includes a substrate and a first electrostatic discharge protection device over the substrate. The first electrostatic discharge protection device includes a buried layer over the substrate. The buried layer has a first region having a first doping concentration and a second region having a second doping concentration. The first doping concentration is greater than the second doping concentration. The first electrostatic discharge protection device includes a first transistor over the buried layer. The first transistor has an emitter coupled to a first cathode terminal of the electrostatic discharge protection clamp. The first electrostatic discharge protection device includes a second transistor over the buried layer. The second transistor has an emitter coupled to a first anode terminal of the electrostatic discharge protection clamp. A collector of the first transistor and a collector of the second transistor are over the first region of the buried layer.