A method of forming a vertical finFET and vertical diode device on the same substrate, including forming a channel layer stack on a heavily doped layer; forming fin trenches in the channel layer stack; oxidizing at least a portion of the channel layer stack inside the fin trenches to form a dummy layer liner; forming a vertical fin in the fin trenches with the dummy layer liner; forming diode trenches in the channel layer stack; oxidizing at least a portion of the channel layer stack inside the diode trenches to form a dummy layer liner; forming a first semiconductor segment in a lower portion of the diode trenches with the dummy layer liner; and forming a second semiconductor segment in an upper portion of the diode trenches with the first semiconductor segment, where the second semiconductor segment is formed on the first semiconductor segment to form a p-n junction.

A method of forming a vertical finFET and vertical diode device on the same substrate, including forming a channel layer stack on a heavily doped layer; forming fin trenches in the channel layer stack; oxidizing at least a portion of the channel layer stack inside the fin trenches to form a dummy layer liner; forming a vertical fin in the fin trenches with the dummy layer liner; forming diode trenches in the channel layer stack; oxidizing at least a portion of the channel layer stack inside the diode trenches to form a dummy layer liner; forming a first semiconductor segment in a lower portion of the diode trenches with the dummy layer liner; and forming a second semiconductor segment in an upper portion of the diode trenches with the first semiconductor segment, where the second semiconductor segment is formed on the first semiconductor segment to form a p-n junction.

A structure includes a substrate and a tunnel field effect transistor (TFET). The TFET includes a source region disposed in the substrate having an overlying source contact, the source region containing first semiconductor material having a first doping type; a drain region disposed in the substrate having an overlying drain contact, the drain region containing second semiconductor material having a second, opposite doping type; and a gate structure that overlies a channel region between the source and the drain. The source region and the drain region are asymmetric with respect to one another such that one contains a larger volume of semiconductor material than the other one. A method is disclosed to fabricate a plurality of the TFETs using a plurality of spaced apart mandrels having spacers. A pair of the mandrels and the associated spacers is processed to form four adjacent TFETs without requiring intervening lithographic processes.

A power semiconductor device includes a silicon carbide substrate and at least a first layer or region formed above the substrate. The silicon carbide substrate has a pattern of pits formed thereon. The device further comprising an ohmic metal disposed at least in the pits to form low-resistance ohmic contacts.

A method of forming a gate spacer in a vertical transistor includes depositing a gate spacer layer on a source layer and a sacrificial gate material on the gate spacer layer; etching a trench through the sacrificial gate material and the gate spacer and forming an epitaxial channel within the trench; removing a portion of the sacrificial gate material to expose a portion of the gate spacer layer and leave the sacrificial gate material arranged on sidewalls of the channel; depositing an ultra-low-k spacer material on the gate spacer layer such that the ultra-low-k spacer material contacts a sidewall of the sacrificial gate material; and removing remaining portions of the sacrificial gate material and replacing the sacrificial gate material with a metal gate.

Semiconductor dies with recesses, associated leadframes, and associated systems and methods are disclosed. A semiconductor system in accordance with one embodiment includes a semiconductor die having a first surface and a second surface facing opposite from the first surface, with the first surface having a die recess. The system can further include a support paddle carrying the semiconductor die, with at least part of the support paddle being received in the die recess. In particular embodiments, the support paddle can form a portion of a leadframe. In other particular embodiments, the support paddle can include a paddle surface that faces toward the semiconductor die and has an opening extending through the paddle surface and through the support paddle.

An integrated circuit is provided having a semiconductor structure, the semiconductor structure including a vertical field-effect transistor; and a diode wherein the vertical field-effect transistor and the diode are co-integrated in the semiconductor structure.

A nitride compound semiconductor has a substrate and a nitride compound semiconductor stack on the substrate. The nitride compound semiconductor stack includes a multilayer buffer layer, a channel layer on this multilayer buffer layer, and an electron supply layer on this channel layer. A recess extends from the surface of the electron supply layer through the channel layer and the multilayer buffer layer. A heat dissipation layer in this recess is contiguous to the multilayer buffer layer and the channel layer and has a higher thermal conductivity than the multilayer buffer layer.

A layout design of a standard cell for a set of masks includes a first gate pad layout pattern, a second gate pad layout pattern immediately adjacent to the first gate pad layout pattern, and a third gate pad layout pattern immediately adjacent to the second gate pad layout pattern. Each gate pad layout pattern has first and second sides extending along a first direction, the second side further along a second direction than the first side. A first gate pad pitch is a distance between first sides of the first and second gate pad layout patterns and has a value different from that of a second gate pad pitch that is a distance between first sides of the second and third gate pad layout patterns. Each gate pad pattern is usable for forming a gate pad surrounding a set of channel structures.

A method for forming a semiconductor device structure is provided. The method includes performing a first plasma etching process on a substrate to form a first trench in the substrate. The method includes removing a second portion of the substrate under the bottom surface to form a second trench under and connected to the first trench. The second trench surrounds a third portion of the substrate under the first portion. The third portion has a first sidewall. The first sidewall is inclined relative to the top surface at a second angle, and the first angle is greater than the second angle. The method includes forming an isolation structure in the first trench and the second trench. The method includes forming a gate insulating layer over the top surface and the first inclined surface. The method includes forming a gate over the gate insulating layer and the isolation structure.