A method of forming a variable spacer in a vertical transistor device includes forming a first source/drain of a first transistor on a substrate; forming a second source/drain of a second transistor on the substrate adjacent to the first source/drain, an isolation region arranged in the substrate between the first source/drain and the second source/drain; depositing a spacer material on the first source/drain; depositing the spacer material on the second source/drain; forming a first channel extending from the first source drain and through the spacer material; forming a second channel extending from the second source/drain and through the spacer material; wherein the spacer material on the first source/drain forms a first spacer and the spacer material on the second source/drain forms a second spacer, the first spacer being different in thickness than the second spacer.

According to an exemplary embodiment, a method of forming a vertical structure is provided. The method includes the following operations: providing a substrate; providing the vertical structure having a source, a channel, and a drain over the substrate; shrinking the source and the channel by oxidation; forming a metal layer over the drain of the vertical structure; and annealing the metal layer to form a silicide over the drain of the vertical structure.

Stacked devices and circuits formed by stacked devices are described. In accordance with some embodiments, a semiconductor post extends vertically from a substrate. A first source/drain region is in the semiconductor post. A first gate electrode layer laterally surrounds the semiconductor post and is vertically above the first source/drain region. A first gate dielectric layer is interposed between the first gate electrode layer and the semiconductor post. A second source/drain region is in the semiconductor post and is vertically above the first gate electrode layer. The second source/drain region is connected to a power supply node. A second gate electrode layer laterally surrounds the semiconductor post and is vertically above the second source/drain region. A second gate dielectric layer is interposed between the second gate electrode layer and the semiconductor post. A third source/drain region is in the semiconductor post and is vertically above the second gate electrode layer.

A method of fabricating a vertical field effect transistor comprising that includes forming openings through a spacer material to provide fin structure openings to a first semiconductor material, and forming an inner spacer liner on sidewalls of the fin structure openings. A channel semiconductor material is epitaxially formed on a surface of the first semiconductor material filling at least a portion of the fin structure openings. The spacer material is recessed with an etch that is selective to the inner spacer liner to form a first spacer. The inner spacer liner is removed selectively to the channel semiconductor material. A gate structure on the channel semiconductor material, and a second semiconductor material is formed in contact with the channel semiconductor material.

A semiconductor device includes a first a first transistor configured to operate at a first threshold voltage level. The first transistor includes a first gate structure and a first drain terminal electrically coupled to the first gate structure. The semiconductor device also includes a second transistor configured to operate at a second threshold voltage level different from the first threshold voltage level, The second transistor includes a second source terminal and a second gate structure electrically coupled to the first gate structure. The first gate structure and the second gate structure comprise a first component in common, and the second gate structure further includes at least one extra component disposed over the first component. The number of the at least one extra component is determined by a desired voltage difference between the first threshold voltage level and the second threshold voltage level.

Logic circuits, or logic gates, are disclosed comprising vertical transport field effect transistors and one or more active gates, wherein the number of C.sub.PP's for the logic circuit, in isolation, is equal to the number of active gates. The components of the logic circuit can be present in at least three different vertical circuit levels, including a circuit level comprising at least one horizontal plane passing through a conductive element that provides an input voltage to the one or more gate structures and another conductive element that provides an output voltage of the logic circuit, and another circuit level that comprises a horizontal plane passing through a conductive bridge from the N output to P output of the field effect transistors. Such logic circuits can include single-gate inverters, two-gate inverters, NOR2 logic gates, and NAND3 logic gates, among other more complicated logic circuits.

A method for producing a semiconductor device includes forming a semiconductor-pillar on a substrate and forming a laminated-structure of at least two composite layers, each including a metal layer and a semiconductor layer in contact with the metal layer, the semiconductor layer containing donor or acceptor atoms, and two interlayer insulating layers sandwiching the composite layers, such that a side surface of at least one of the two interlayer insulating layers is separated from a side surface of the semiconductor pillar. The laminated-structure surrounds the semiconductor pillar. A first heat treatment causes a reaction between the metal layer and the semiconductor layer to form an alloy layer, and brings the alloy layer into contact with the side surface of the semiconductor pillar. A second heat treatment to expands the alloy layer into the semiconductor pillar and diffuses dopant atoms into the semiconductor pillar to form an impurity region therein.

A method of fabricating a vertical field effect transistor comprising that includes forming openings through a spacer material to provide fin structure openings to a first semiconductor material, and forming an inner spacer liner on sidewalls of the fin structure openings. A channel semiconductor material is epitaxially formed on a surface of the first semiconductor material filling at least a portion of the fin structure openings. The spacer material is recessed with an etch that is selective to the inner spacer liner to form a first spacer. The inner spacer liner is removed selectively to the channel semiconductor material. A gate structure on the channel semiconductor material, and a second semiconductor material is formed in contact with the channel semiconductor material.

A semiconductor device includes an n-type vertical field-effect transistor (FET) that includes: a first source/drain feature disposed in a substrate; a first vertical bar structure that includes a first sidewall and a second sidewall disposed over the substrate; a gate disposed along the first sidewall of the first vertical bar structure; a second vertical bar structure electrically coupled to the first vertical bar structure; and a second source/drain feature disposed over the first vertical bar structure; and a p-type FET that includes; a third source/drain feature disposed in the substrate; a third vertical bar structure that includes a third sidewall and a fourth sidewall disposed over the substrate; the gate disposed along the third sidewall of the third vertical bar structure; a fourth vertical bar structure electrically coupled to the third vertical bar structure; and a fourth source/drain feature disposed over the third vertical bar structure.

A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET uses a gate-all-around (GAA) device architecture having a cylindrical structure that extends above the surface of a doped well formed in a silicon substrate. The cylindrical structure includes a lower drain region, a channel, and an upper source region, which are grown epitaxially from the doped well. The channel is made of intrinsic silicon, while the source and drain regions are doped in-situ. An annular gate surrounds the channel, capacitively controlling current flow through the channel from all sides. The source is electrically accessible via a front side contact, while the drain is accessed via a backside contact that provides low contact resistance and also serves as a heat sink. Reliability of vertical TFET integrated circuits is enhanced by coupling the vertical TFETs to electrostatic discharge (ESD) diodes.