A Tunnel Field-Effect Transistor (TFET) is provided comprising a source-channel-drain structure of a semiconducting material. The source-channel-drain structure comprises a source region being n-type or p-type doped, a drain region oppositely doped than the source region and an intrinsic or lowly doped channel region situated between the source region and the drain region. The TFET further comprises a reference gate structure covering the channel region and a source-side gate structure aside of the reference gate structure wherein the work function and/or electrostatic potential of the source-side gate structure and the reference work function and/or electrostatic potential of the reference gate structure are selected for allowing the tunneling mechanism of the TFET device in operation to occur at the interface or interface region between the source-side gate structure and the reference gate structure in the channel region.

A method of fabricating a semiconductor transistor and the semiconductor transistor include a source region and a drain region within a substrate. The method includes forming a gate above the substrate, forming a source contact above the source region and a drain contact above the drain region, and forming air spacers within a dielectric between the gate and each of the source contact and the drain contact. Metal caps are formed on the source contact and the drain contact, and a gate cap is formed between the dielectric and at least a portion of a bottom surface of higher-level contacts, which are contacts formed above the source contact and the drain contact.

Unfilled gaps are provided as spacers between gate stacks and electrically conductive source/drain contacts to reduce parasitic capacitance in CMOS structures. Sidewall spacers are removed partially or entirely from portions of the gate stacks and replaced by materials such as amorphous semiconductor materials. Source/drain contacts subsequently formed on source/drain regions adjoin the spacer replacement material. Selective removal of the spacer replacement material leaves unfilled gaps between the source/drain contacts and the gate stacks. The unfilled gaps are then sealed by a dielectric layer that leaves the gaps substantially unfilled.

A semiconductor structure includes a substrate, at least one first gate structure, at least one source drain structure, at least one bottom conductor, and a first dielectric layer. The first gate structure is present on the substrate. The source drain structure is present on the substrate. The bottom conductor is electrically connected to the source drain structure. The bottom conductor has an upper portion and a lower portion between the upper portion and the source drain structure, and a gap is at least present between the upper portion of the bottom conductor and the first gate structure. The first dielectric layer is at least present between the lower portion of the bottom conductor and the first gate structure.

A semiconductor device includes a substrate including a first fin element, a second fin element, and a third fin element. A first source/drain epitaxial feature is disposed over the first and second fin elements. A first portion of the first source/drain epitaxial feature disposed on the first fin element and a second portion of the first source/drain epitaxial feature disposed on the second fin element merge at a merge point. A second source/drain epitaxial feature is disposed over the third fin element. A first sidewall of the second source/drain epitaxial feature interfaces a first third-fin spacer disposed along a first sidewall of the third fin element. A second sidewall of the second source/drain epitaxial feature interfaces a second third-fin spacer disposed along a second sidewall of the third fin element. The merge point has a first height less than a second height of the first third-fin spacer.

There is provided a semiconductor device capable of enhancing device performance by variably adjusting threshold voltage of a transistor having gate-all-around structure. The semiconductor device includes a substrate including a first region and a second region, a first wire pattern provided on the first region of the substrate and spaced apart from the substrate, a second wire pattern provided on the second region of the substrate and spaced apart from the substrate, a first gate insulating film surrounding a perimeter of the first wire pattern, a second gate insulating film surrounding a perimeter of the second wire pattern, a first gate electrode provided on the first gate insulating film, intersecting with the first wire pattern, and including a first metal oxide film therein, a second gate electrode provided on the second gate insulating film and intersecting with the second wire pattern, a first gate spacer on a sidewall of the first gate electrode, and a second gate spacer on a sidewall of the second gate electrode.

A memory device with a dielectric layer or an air gap between contacts and a method of making the same are disclosed. The method comprises a series of steps including: forming a plurality of conductive lines having trenches therebetween; forming a contact layer in the trench; and forming a dielectric layer interposed in the contact layer and configured to divide the contact layer into two contacts. The method also comprises removing the dielectric layer to form a space and forming a cap layer over the contacts to form an air gap therein. The method further comprises forming a second air gap between the conductive fine and the contact.

A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a substrate, a gate structure, a first dielectric layer and two air gaps. The gate structure is disposed on the substrate. The gate structure has two opposite side walls. The gate structure comprises a U-shaped structure and a metal gate electrode. The U-shaped structure defines an opening toward upside, and comprises a work function layer. The metal gate electrode is disposed in the opening defined by the U-shaped structure. A level of a top surface of the U-shaped structure is lower than a level of a top surface of the metal gate electrode. The first dielectric layer is disposed on the substrate adjacent to the gate structure. Each of the two air gaps is formed between the first dielectric layer and one of the two opposite side walls of the gate structure.

An image-capturing device uses a light reflecting member to redirect an exterior light image toward a lens module in order to focus the light image onto an image-capturing unit. The image-capturing device includes a rotating unit for driving the light-reflecting member to rotate within a limited range in such a manner that the image-capturing device can capture at least two light images of different photo-ing areas and combine them into one single combined image without a need of moving the image-capturing unit and the lens module. When a user takes a panoramic or wide-ranged picture, he/she doesn't need to move the whole image-capturing device, but only needs to stand at the same position, faces the same direction and simply pushes the shutter button, and then the image-capturing device will automatically capture light images of different photo-ing areas and then integrate them into one single panoramic or wide-ranged picture.

A vertical transistor has a first air-gap spacer between the gate and the bottom source/drain, and a second air-gap spacer between the gate and the contact to the bottom source/drain. A dielectric layer disposed between the gate and the contact to the top source/drain decreases parasitic capacitance and inhibits electrical shorting.