A semiconductor device includes a plurality of semiconductor layers arranged one above another, and source/drain epitaxial regions on opposite sides of the plurality of semiconductor layers. The semiconductor device further includes a gate structure surrounding each of the plurality of semiconductor layers. The gate structure includes interfacial layers respectively over the plurality of semiconductor layers, a high-k dielectric layer over the interfacial layers, and a gate metal over the high-k dielectric layer. The gate structure further includes gate spacers spacing apart the gate structure from the source/drain epitaxial regions. A top position of the high-k dielectric layer is lower than top positions of the gate spacers.

After forming a source/drain contact including a source/drain contact liner and a source/drain contact conductor surrounded by the source/drain contact liner to contact one of source/drain regions formed on opposite sides of a functional gate structure, vertical portions of the source/drain contact liner are recessed partially or completely to provide a cavity between the functional gate structure and the source/drain contact conductor. An etch resistant layer is deposited over the functional gate structure, each source/drain contact and each cavity to pinch off each cavity, thus forming an airgap between the functional gate structure and each source/drain contact.

A semiconductor structure including one or more semiconductor devices on a wafer. The one or more devices having source/drain junctions. The semiconductor structure further includes a recessed middle-of-line (MOL) oxide layer, and an air-gap oxide layer including one or more introduced air-gaps. The air-gap oxide layer is positioned over the one or more semiconductor devices and the MOL oxide layer. A nitride layer is positioned over the one or more semiconductor devices. Trenches are formed through the nitride layer down to the source/drain junctions. A silicide fills the trenches.

A semiconductor structure formed based on selectively recessing a middle-of-line (MOL) oxide layer of the semiconductor structure including multiple gate stacks formed on a substrate. A cap layer of the multiple gate stacks is selectively recessed. An air-gap oxide layer introducing one or more air-gaps is deposited. Chemical-mechanical planarization (CMP) is performed on the deposited air-gap oxide layer.

A vertical transistor has a first air-gap spacer between a gate and a bottom source/drain region, and a second air-gap spacer between the gate and the contact to the bottom source/drain region. A dielectric layer disposed between the gate and the contact to the top source/drain decreases parasitic capacitance and inhibits electrical shorting.

A vertical transistor has a first air-gap spacer between the gate and the bottom source/drain, and a second air-gap spacer between the gate and the contact to the bottom source/drain. A dielectric layer disposed between the gate and the contact to the top source/drain decreases parasitic capacitance and inhibits electrical shorting.

A semiconductor device includes a gate positioned on a substrate; a nanosheet that extends through the gate, protrudes from a sidewall of the gate, and forms a recess between the substrate and the nanosheet; a dielectric spacer disposed in the recess; a source/drain contact positioned on a source/drain disposed on the substrate adjacent to the gate; an air gap spacer positioned along the sidewall of the gate and in contact with a dielectric material disposed on the nanosheet, the air gap spacer being in contact with the source/drain contact; and an interlayer dielectric (ILD) disposed on the air gap spacer.

A semiconductor device that includes a gate structure on a channel region of a semiconductor device. Source and drain regions may be present on opposing sides of the channel region. The semiconductor device may further include a composite gate sidewall spacer present on a sidewall of the gate structure. The composite gate sidewall spacer may include a first composition portion having an air gap encapsulated therein, and a second composition portion that is entirely solid and present atop the first composition portion.

A semiconductor device that includes a gate structure on a channel region of a semiconductor device. Source and drain regions may be present on opposing sides of the channel region. The semiconductor device may further include a composite gate sidewall spacer present on a sidewall of the gate structure. The composite gate sidewall spacer may include a first composition portion having an air gap encapsulated therein, and a second composition portion that is entirely solid and present atop the first composition portion.

An integrated circuit device includes a fin type active area protruding from a substrate and having an upper surface at a first level; a nanosheet extending in parallel to the upper surface of the fin type active area and comprising a channel area, the nanosheet being located at a second level spaced apart from the upper surface of the fin type active area; a gate disposed on the fin type active area and surrounding at least a part of the nanosheet, the gate extending in a direction crossing the fin type active area; a gate dielectric layer disposed between the nanosheet and the gate; a source and drain region formed on the fin type active area and connected to one end of the nanosheet; a first insulating spacer on the nanosheet, the first insulating spacer covering sidewalls of the gate; and a second insulating spacer disposed between the gate and the source and drain region in a space between the upper surface of the fin type active area and the nanosheet, the second insulating spacer having a multilayer structure.