A semiconductor device includes a first and second fin-shaped semiconductor layers on a substrate. A first insulating film is around the first and second fin-shaped layers. A first and second pillar-shaped semiconductor layers reside on the first and second fin-shaped layers, respectively. A width of a bottom of the first pillar-shaped semiconductor layer is equal to a width of a top of the first fin-shaped semiconductor layer, and a width of a bottom of the second pillar-shaped semiconductor layer is equal to the width of a top of the second fin-shaped semiconductor layer. First and second gate insulating films and first and second metal gate electrodes reside around the first and second pillar-shaped layers, respectively. A metal gate line is connected to the first and second metal gate electrodes and extends in a direction perpendicular to the first and second fin-shaped layers.

A method of forming a MOSFET device is provided including: providing an SOI wafer; forming a dummy gate oxide and dummy gates on portions of the SOI layer that serve as channel regions of the device; forming spacers and doped source/drain regions in the SOI layer on opposite sides of the dummy gates; depositing a gap fill dielectric; removing the dummy gates/gate oxide; recessing areas of the SOI layer exposed by removal of the dummy gates forming one or more u-shaped grooves that extend part-way through the SOI layer such that a thickness of the SOI layer remaining in the channel regions is less than a thickness of the SOI layer in the doped source/drain regions under the spacers; and forming u-shaped replacement gate stacks in the u-shaped grooves such that u-shaped channels are formed in fully depleted regions of the SOI layer adjacent to the u-shaped replacement gate stacks.

A semiconductor device including: a first conductivity type transistor and a second conductivity type transistor, wherein each of the first conductivity type transistor and the second conductivity type includes agate insulating film formed on a base, a metal gate electrode formed on the gate insulating film, and side wall spacers formed at side walls of the metal gate electrode, wherein the gate insulating film is made of a high dielectric constant material, and wherein offset spacers are formed between the side walls of the metal gate electrode and the inner walls of the side wall spacers in any one of the first conductivity type transistor and the second conductivity type transistor, or offset spacers having different thicknesses are formed in the first conductivity type transistor and the second conductivity type transistor.

A method of fabricating a vertical field effect transistor comprising that includes forming openings through a spacer material to provide fin structure openings to a first semiconductor material, and forming an inner spacer liner on sidewalls of the fin structure openings. A channel semiconductor material is epitaxially formed on a surface of the first semiconductor material filling at least a portion of the fin structure openings. The spacer material is recessed with an etch that is selective to the inner spacer liner to form a first spacer. The inner spacer liner is removed selectively to the channel semiconductor material. A gate structure on the channel semiconductor material, and a second semiconductor material is formed in contact with the channel semiconductor material.

A highly reliable semiconductor device including an oxide semiconductor is provided by preventing a change in its electrical characteristics. A semiconductor device which includes a first oxide semiconductor layer which is in contact with a source electrode layer and a drain electrode layer and a second oxide semiconductor layer which serves as a main current path (channel) of a transistor is provided. The first oxide semiconductor layer serves as a buffer layer for preventing a constituent element of the source and drain electrode layers from diffusing into the channel. By providing the first oxide semiconductor layer, it is possible to prevent diffusion of the constituent element into an interface between the first oxide semiconductor layer and the second oxide semiconductor layer and into the second oxide semiconductor layer.

An active matrix substrate (100) includes a display region (R1) in which a plurality of pixels are provided and a frame region (R2) provided around the display region, the frame region including a plurality of peripheral circuit TFTs (5) which are constituents of a driving circuit, wherein each of the plurality of peripheral circuit TFTs includes a gate electrode (12), a source electrode (16), a drain electrode (18), and an oxide semiconductor layer (14), and in at least some of the plurality of peripheral circuit TFTs, a source connecting region (Rs) that is a connecting region between the oxide semiconductor layer and the source electrode and a drain connecting region (Rd) that is a connecting region between the oxide semiconductor layer and the drain electrode are asymmetrically provided.

A junction field effect transistor (JFET) comprises an insulating carrier substrate, a base semiconductor substrate formed on the insulating carrier substrate and a gate region formed on the base semiconductor substrate. The gate region forms a junction with the base semiconductor substrate. The JFET further comprises a first source/drain region formed on the base semiconductor substrate and located on a first side of the gate region and a second source/drain region formed on the base semiconductor substrate and located on a second side of the gate region. A gate stack is deposited on the gate region, a first source/drain stack is deposited on the first source/drain region and a second source/drain stack is deposited on the second source/drain region. At least one of the gate stack, first source/drain stack and second source/drain stack overlaps onto another one of the gate stack, first source/drain stack and second source/drain stack.

One illustrative method disclosed includes, among other things, forming a vertically oriented semiconductor structure above a doped well region defined in a semiconductor substrate, the semiconductor structure comprising a lower source/drain region and an upper source/drain region, wherein the lower source/drain region physically contacts the upper surface of the substrate, forming a counter-doped isolation region in the substrate, forming a metal silicide region in the substrate above the counter-doped isolation region, wherein the metal silicide region is in physical contact with the lower source/drain region, and forming a lower source/drain contact structure that is conductively coupled to the metal silicide region.

A method of forming a contact in a semiconductor device includes forming a first gate and a second gate on a substrate; removing an interlayer dielectric (ILD) material arranged between the first gate and the second gate to form a trench that extends from a surface of the first gate and a surface of the second gate to the substrate; depositing a liner along a sidewall of the trench and an endwall of the trench in contact with the substrate; depositing by a physical vapor deposition method (PVD) a layer of metal on a surface of the first gate and a surface of the second gate; and heating to reflow metal from the layer of metal on the surface of the first gate and the second gate into the trench and form the contact.

Embodiments of the present invention provide a structure and method of minimizing stress relaxation during fin formation. Embodiments may involve forming a looped spacer on an upper surface of a substrate and adjacent to at least a sidewall of a mandrel. The mandrel may be removed, leaving the looped spacer on the substrate. An exposed portion of the substrate may be removed to form a looped fin below the looped spacer. The spacer may be removed, leaving a looped fin. A looped fin formation may reduce stress relaxation compared to conventional fin formation methods. Embodiments may include forming a gate over a looped portion of a looped fin. Securing a looped portion in position with a gate may decrease stress relaxation in the fin. Thus, a looped fin with a looped portion of the looped fin under a gate may have substantially reduced stress relaxation compared to a conventional fin.