A semiconductor device includes a vertical MOS transistor with a plurality of parallel RESURF drain trenches separated by a constant spacing in a vertical drain drift region. The vertical MOS transistor has chamfered corners; each chamfered corner extends across at least five of the drain trenches. A RESURF termination trench surrounds the drain trenches, separated from sides and ends of the drain trenches by distances which are functions of the drain trench spacing. At the chamfered corners, the termination trench includes external corners which extend around an end of a drain trench which extends past an adjacent drain trench, and includes internal corners which extend past an end of a drain trench which is recessed from an adjacent drain trench. The termination trench is separated from the drain trenches at the chamfered corners by distances which are also functions of the drain trench spacing.

First and second transistors with different electrical characteristics are supported by a substrate having a first-type dopant. The first transistor includes a well region within the substrate having the first-type dopant, a first body region within the well region having a second-type dopant and a first source region within the first body region and laterally offset from the well region by a first channel. The second transistor includes a second body region within the semiconductor substrate layer having the second-type dopant and a second source region within the second body region and laterally offset from material of the substrate by a second channel having a length greater than the length of the first channel. A gate region extends over portions of the first and second body regions for the first and second channels, respectively.

Disclosed is a transistor device. The transistor device includes: a semiconductor body with an active region and a pad region; at least one transistor cell including a gate electrode dielectrically insulated from a body region by a gate dielectric, wherein the body region is arranged in the active region; an electrode layer arranged above the pad region and dielectrically insulated from the pad region by a further dielectric; and a gate pad arranged above the electrode layer and electrically connected to the electrode layer and the gate electrode of the at least one transistor cell. A thickness of the further dielectric is equal to or less than a thickness of the gate dielectric.

A semiconductor device includes a semiconductor substrate including, between a bottom side and a top side, a first trench and a second trench extending in a vertical direction, and a contact groove arranged between the first trench and the second trench. The contact groove has a longitudinal extension in a plane perpendicular to the vertical direction. The longitudinal extension of the contact groove at least partially has a wave-shape.

A semiconductor device comprises a silicon carbide based semiconductor layer structure that comprises an active region. A gate trench is provided in an upper portion of the semiconductor layer structure, the gate trench having a first rounded lower corner and a second rounded lower corner. A gate electrode is provided in the gate trench. Within the active region, an upper surface of the gate electrode is below or coplanar with an upper surface of the semiconductor layer structure.

An electrostatic discharge protection device includes a substrate, a well region of a first conductivity type in the substrate, a drain field region and a source field region of a second conductivity type in the well region, a gate structure on the well region and between the drain field region and the source field region, a drain contact region and a source contact region of the second conductivity type respectively in the drain field region and the source field region, a first isolation region in the drain field region and between the drain contact region and the gate structure, and a drain doped region of the first conductivity in the drain field region and between a portion of a bottom surface of the drain contact region and the drain field region.

A semiconductor device has an active region through which a main current flows, a gate ring region surrounding a periphery of the active region, a source ring region surrounding a periphery of the gate ring region, and a termination region surrounding a periphery of the source ring region. The semiconductor device has a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, and further, in the active region, first semiconductor regions of the first conductivity type, a gate insulating film, first gate electrodes, an interlayer insulating film, a first first-electrode, a first plating film, and a second electrode. The semiconductor device has, in the source ring region, a second first-electrode provided at a surface of the second semiconductor layer, and a second plating film provided on the second first-electrode.

A semiconductor structure that includes at least one lateral diffusion field effect transistor is described. The structure includes a source contact and a gate shield that enables the line width of an ohmic region that electrically connects the source/body region to the gate shield to be smaller than the minimum contact feature size. The gate shield defines a bottom recess for forming a narrower bottom portion of the source contact, and a section that flares outward with distance from the ohmic region to extend above and laterally beyond the ohmic region. By providing a wider area for the source contact, the flared portion of the gate shield allows the portion of the gate shield that contacts the ohmic region to be narrower than the minimum contact feature size. As a result, the cell pitch of the lateral diffusion field effect transistor can be reduced.

A semiconductor device includes an N+ type substrate, an N type layer disposed on a first surface of the N+ type substrate and having a trench opened to a surface opposite to the surface facing the N+ type substrate, a P type region disposed in the N type layer and disposed on a side surface of the trench, a gate electrode disposed in the trench, and a source electrode and a drain electrode insulated from the gate electrode. The N type layer includes a P type shield region covering a bottom surface and an edge of the trench.

A high voltage superjunction MOSFET includes a semiconductor substrate and a semiconductor layer having columns of first and second conductivity. A buffer layer of the first conductivity is between the semiconductor substrate and semiconductor layer. A plug region of the second conductivity is formed at a semiconductor layer surface and extends to the columns. A source/drain region is formed at the semiconductor layer surface and is connected to the plug region. The source/drain region has a concentration of the first conductivity between about 110.sup.19 cm.sup.3 and 1.510.sup.20 cm.sup.3. A body region of the second conductivity is between the source/drain region and the first column and is connected to the plug region. A gate trench is formed in the semiconductor layer surface and extends toward the first column and has a trench gate electrode disposed therein. A dielectric layer separates the trench gate electrode from the first column.