A semiconductor device includes a fin-shaped silicon layer on a silicon substrate. A first insulating film is around the fin-shaped silicon layer and a pillar-shaped silicon layer is on the fin-shaped silicon layer. A gate insulating film is around the pillar-shaped silicon layer. A metal gate electrode is around the gate insulating film and a metal gate line is connected to the metal gate electrode. A metal gate pad is connected to the metal gate line, and a width of the metal gate electrode and a width of the metal gate pad is larger than a width of the metal gate line.

A method for manufacturing a semiconductor device having a MOS gate structure includes forming a device structure on a semiconductor substrate; forming an interlayer dielectric to cover the device structure; forming a contact hole through the interlayer dielectric; forming a transition metal film (e.g., Ni) on a portion of the semiconductor substrate exposed by the contact hole; (e) forming a metal film (e.g., Ti) on the entire surface of the semiconductor substrate; forming an oxide film in the surface of the metal film; selectively removing the metal film in which the oxide film has been formed, to thereby expose the transition metal film; and (h) exposing, to a hydrogen plasma atmosphere, the semiconductor substrate in which the transition metal film and the oxide film have been exposed, to thereby cause the transition metal film to generate heat and react with the semiconductor substrate and form an ohmic contact there between.

A method of manufacturing a semiconductor device includes forming a first trench in a semiconductor substrate from a first side, forming a semiconductor layer adjoining the semiconductor substrate at the first side, the semiconductor layer capping the first trench at the first side, and forming a contact at a second side of the semiconductor substrate opposite to the first side.

A method for producing a semiconductor device includes forming a first insulating film around a fin-shaped semiconductor layer and forming a pillar-shaped semiconductor layer and forming a second diffusion layer in an upper portion of the fin-shaped semiconductor layer and a lower portion of the pillar-shaped semiconductor layer. A metal-semiconductor compound is formed on the second diffusion layer. A first metal is deposited to form a gate electrode and a gate line. Second and third metal films are deposited to form a first contact in which the second metal film surrounds a sidewall of an upper portion of the pillar-shaped semiconductor layer, and a second contact connects an upper portion of the first contact and an upper portion of the pillar-shaped semiconductor layer. A third contact is formed on the gate line.

A semiconductor device includes a pillar-shaped semiconductor layer and a first gate insulating film around the pillar-shaped semiconductor layer. A metal gate electrode is around the first gate insulating film and a metal gate line is connected to the gate electrode. A second gate insulating film is around a sidewall of an upper portion of the pillar-shaped semiconductor layer and a first contact made of a second metal surrounds the second gate insulating film. An upper portion of the first contact is electrically connected to an upper portion of the pillar-shaped semiconductor layer, and a third contact resides on the metal gate line. A lower portion of the third contact is made of the second metal.

A vertical transistor has a first air-gap spacer between a gate and a bottom source/drain region, and a second air-gap spacer between the gate and the contact to the bottom source/drain region. A dielectric layer disposed between the gate and the contact to the top source/drain decreases parasitic capacitance and inhibits electrical shorting.

A vertical transistor has a first air-gap spacer between the gate and the bottom source/drain, and a second air-gap spacer between the gate and the contact to the bottom source/drain. A dielectric layer disposed between the gate and the contact to the top source/drain decreases parasitic capacitance and inhibits electrical shorting.

A method for producing a semiconductor device includes forming a first insulating film around a fin-shaped semiconductor layer and forming a pillar-shaped semiconductor layer and forming a second diffusion layer in an upper portion of the fin-shaped semiconductor layer and a lower portion of the pillar-shaped semiconductor layer. A metal-semiconductor compound is formed on the second diffusion layer. A first metal is deposited to form a gate electrode and a gate line. Second and third metal films are deposited to form a first contact in which the second metal film surrounds a sidewall of an upper portion of the pillar-shaped semiconductor layer, and a second contact connects an upper portion of the first contact and an upper portion of the pillar-shaped semiconductor layer. A third contact is formed on the gate line.

A semiconductor device which solves the following problem of a super junction structure: due to a relatively high concentration in the body cell region (active region), in peripheral areas (peripheral regions or junction end regions), it is difficult to achieve a breakdown voltage equivalent to or higher than in the cell region through a conventional junction edge terminal structure or resurf structure. The semiconductor device includes a power MOSFET having a super junction structure formed in the cell region by a trench fill technique. Also, super junction structures having orientations parallel to the sides of the cell region are provided in a drift region around the cell region.

Trenches and n.sup.+ high impurity concentration regions are formed in a first principal surface side of a silicon carbide semiconductor substrate. In the n.sup.+ high impurity concentration regions, third n-type regions that respectively surround first p.sup.+ base regions contacting a p-type base layer and have a higher impurity concentration than the n.sup.+ high impurity concentration regions, as well as fourth n-type regions that respectively surround second p.sup.+ base regions formed at the bottoms of the trenches and also have a higher impurity concentration than the n.sup.+ high impurity concentration regions, are formed.