A vertical transistor and the fabrication method. The transistor comprises a first surface and a second surface that is opposite to the first surface. A drift region of the first doping type, this drift region is located between the first surface and the second surface; at least one source region of the first doping type and the source region being located between the drift region and the first surface, with a first dielectric layer located between adjacent source regions; at least one drain region with said first doping type and said drain region being located between said drift region and said second surface, a gate being provided between adjacent drain regions. Said gate includes a gate electrode and a gate dielectric layer disposed between said gate electrode and said drift region, and the second dielectric layer being positioned between said gate electrode and said second surface.

An integrated power transistor circuit includes a contact structure with a first section and a second section. The first section contacts doped regions of transistor cells in a cell array. The second section includes one or more first subsections which adjoin the first section and extend beyond the cell array in the region of selected transistor cells. A second subsection adjoins the one or more first subsections and forms a tapping line, for example for making contact with source regions of power transistor cells. In the region of the cell array, an electrode structure rests on the contact structure. This electrode structure is absent over the second section. The tapping line can thus be formed at a short distance from the electrode structure, with the result that the active chip area is only insubstantially reduced by the tapping line.

An IGBT device and a method for packaging a whole-wafer IGBT chip. The IGBT device comprises: an entire wafer IGBT chip, the upper surface thereof comprising a central gate connection zone and a plurality of emitter connection zones surrounding the central gate connection zone, and the lower surface thereof comprising a collecting zone, wherein the emitter connection zones located on the surface of a failure cellular zone of the chip are thinned; a collector washer which is fixed on the lower surface of the chip, and an emitter washer which is fixed on the upper surface of the chip; a collector electrode which is electrically contacted with the collector washer, and an emitter electrode which is electrically contacted with the emitter washer; and a gate leading wire which is connected to the central gate connection zone.

In an active region, p.sup.+ regions are selectively disposed in a surface layer of an n.sup. drift layer on an n.sup.+ semiconductor substrate. A p-base layer is disposed on surfaces of the n.sup. drift layer and the P.sup.+ regions, and an MOS structure is disposed on the p-base layer. In another portion of the active region, a p.sup.+ region is disposed to be in contact with the source electrode on the p.sup.+ regions. In a breakdown voltage structure region (100), a JTE structure having at least a P.sup. region is disposed separately from the P.sup.+ regions and the p-base layer, to surround the active region. The P.sup. region is electrically in contact with the P.sup.+ region in a portion in which the MOS structure is not formed, in the vicinity of the boundary between the active region and the breakdown voltage structure region.

In a semiconductor device, a lightly doped second semiconductor layer of a first conductive type is joined with a heavily doped first semiconductor layer of the first conductive type. A power transistor having a first conductive type channel and a transistor are formed in surface regions of the second semiconductor layer, respectively. A first diffusion layer of a second conductive type is formed in a surface region of the second semiconductor layer to provide a boundary between the power transistor and the transistor. The first semiconductor layer functions as a drain of the power transistor. The first diffusion layer region is set to the same voltage as that of the drain.

A SiO.sub.2 layer is formed at a middle of a Si pillar. An opening is formed in a gate insulating layer and a gate conductor layer in a peripheral portion that includes a side surface of the SiO.sub.2 layer. Two stacks of layers, each stack being constituted by a Ni layer, a poly-Si layer containing a donor or acceptor impurity atom, and a SiO.sub.2 layer, are formed in a peripheral portion of the opening, and heat treatment is performed to silicidate the poly-Si layers into NiSi layers. The NiSi layers protrude and come into contact with the side surface of the Si pillar by silicidation, and a donor or acceptor impurity atom diffuses from the NiSi layers into the Si pillar. Thus an N.sup.+ region and a P.sup.+ region serving as a source and a drain of surrounding gate MOS transistors are respectively formed above and under the SiO.sub.2 layer.

A first stack of alternating layers including first electrically insulating layers and first sacrificial material layers is formed with first stepped surfaces. First memory openings can be formed in a device region outside of the first stepped surfaces, and first support openings can be formed through the first stepped surfaces. The first memory openings and the first support openings can be filled with a sacrificial fill material. A second stack of alternating layers including second electrically insulating layers and second sacrificial material layers can be formed over the first stack. Inter-stack memory openings including the first memory openings can be formed in the device region, and inter-stack support openings including the first support openings can be formed in a steppes surface region. Memory stack structures and support pillar structure are simultaneously formed in the inter-stack memory openings and the inter-stack support openings, respectively.

A semiconductor device includes a first semiconductor layer of a first conductivity type formed on one side of a semiconductor substrate; a second semiconductor layer of a second conductivity type formed on the first semiconductor layer; a third semiconductor layer of the first conductivity type formed on the second semiconductor layer; an opening part formed by removing part of the first to third semiconductor layers; a gate insulating film formed so as to cover an inner wall of the opening part; a gate electrode formed inside the opening part via the gate insulating film; a source electrode formed on a surface of the third semiconductor layer; a drain electrode connected to a part corresponding to the gate electrode on another side of the semiconductor substrate; and a fourth electrode formed on the another side of the semiconductor substrate at a part corresponding to the source electrode.

First polysilicon (poly-1) is deposited into deep trenches that have been formed in a substrate. A first polysilicon polishing process is performed to planarize the exposed surfaces of the poly-1 so that the surfaces are flush with adjacent surfaces. Then, shallow trenches are formed in the substrate between the deep trenches, and second polysilicon (poly-2) is deposited into the shallow trenches. A second polysilicon polishing process is performed to planarize the exposed surface of the poly-2 so that the surface is flush with adjacent surfaces. Metal contacts to the poly-1 and the poly-2 are then formed.

An electronic device can include a transistor structure, including a patterned semiconductor layer overlying a substrate and having a primary surface. The electronic device can further include first conductive structures within each of a first trench and a second trench, a gate electrode within the first trench and electrically insulated from the first conductive structure, a first insulating member disposed between the gate electrode and the first conductive structure within the first trench, and a second conductive structure within the second trench. The second conductive structure can be electrically connected to the first conductive structures and is electrically insulated from the gate electrode. The electronic device can further include a second insulating member disposed between the second conductive structure and the first conductive structure within the second trench. Processing sequences can be used that simplify formation of the features within the electronic device.