Provided is a semiconductor device including a semiconductor substrate, a plurality of gate electrodes disposed on the upper surface portion of the semiconductor substrate and spaced apart from each other, a plurality of emitter electrodes disposed to be overlapped with each of the plurality of gate electrodes, and a collector electrode disposed on the lower surface of the semiconductor substrate.

According to one embodiment, a semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type, a gate electrode, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, and a second electrode. The gate electrode is located on the first semiconductor region with a gate insulating layer interposed. The second semiconductor region faces the gate electrode via the gate insulating layer. The second semiconductor region includes: a first portion; a second portion located on the first portion and having a higher second-conductivity-type impurity concentration than the first portion; and a third portion positioned between the second portion and the gate electrode and having a higher concentration of a first element than the second portion. The first element is at least one selected from the group consisting of carbon, germanium, antimony, and indium.

A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes a first source layer, a second source layer on the first source layer, a stack on the second source layer, a channel structure passing through the stack and the second source layer, and a common source line passing through the stack and the second source layer. The second source layer includes an air gap and a conductive layer surrounding the air gap.

A semiconductor structure and a forming method thereof are provided. The method for forming a semiconductor structure includes providing a base including a semiconductor substrate and a well region located on a surface of the semiconductor substrate, in which the well region includes a plurality of active pillar columns arranged at intervals along a first direction, and each of the active pillar columns includes a plurality of active pillars arranged at intervals along a second direction, in which the first direction is perpendicular to the second direction; forming a plurality of bit line trenches by etching at least the well region and a partial thickness of the semiconductor substrate at bottoms of the active pillars; and forming buried bit lines in the bit line trenches.

A semiconductor device includes a first impurity region on a substrate; a channel pattern protruding from an upper surface of the substrate, the channel pattern extending in a first direction substantially parallel to the upper surface of the substrate; a second impurity region on the channel pattern, the second impurity region covering an entire upper surface of the channel pattern; a gate structure on a sidewall of the channel pattern and the substrate adjacent to the channel pattern; a first contact pattern on the second impurity region; a second contact pattern that is electrically connected to the gate structure; and a spacer between the first contact pattern and the second contact pattern. The spacer completely surrounds the second contact pattern in plan view, and the first contact pattern partially surrounds the second contact pattern in plan view.

There are provided a semiconductor device, a method of manufacturing the same, and an electronic device including the device. According to an embodiment, the semiconductor device may include a substrate, and a first device and a second device formed on the substrate. Each of the first device and the second device includes a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, and also a gate stack surrounding a periphery of the channel layer. The channel layer of the first device and the channel layer of the second device are substantially co-planar.

A semiconductor device and a method for manufacturing the same. A substrate is provided. A first source-drain layer, a channel layer, and a second source-drain layer are sequentially stacked on the substrate. Both a gate dielectric layer and a gate structure surround the channel layer laterally. The gate structure includes a first portion extending laterally and a second portion extending upward from a periphery of the first portion. A second portion is located at a periphery of the second source-drain layer. A spacer layer is formed at an outer sidewall of the gate structure. The gate structure is etched to reduce a thickness of the gate structure. A sacrificial structure covering the gate structure is formed, and a capping layer covering the second source-drain layer, the sacrificial structure, and the spacer layer is formed. Thereby, the sacrificial structure is located at the periphery of the second source-drain layer and enclosed by the spacer layer. The capping layer is etched to obtain a first contact hole reaching the sacrificial structure. The sacrificial structure at the bottom of the first contact hole is removed to form a gap under the first contact hole. A first contact structure is formed in the first contact hole and the gap. Self-alignment between a bottom of the first contact structure and the gate structure is achieved, and the device has higher reliability.

A semiconductor device having a ring-shaped cell region, a first termination region and a second termination region. The cell region includes a first base region, a source region in the first base region, first and second gate trench structures. The first base region and the source region are sandwiched by the first and second gate trench structure in a plane. The first termination region is surrounded by the ring-shaped cell region in the plane. The second termination region surrounds the ring-shaped cell region in the plane. The first termination region has a round-shaped source trench structure including a source electrode filling in a source trench with a source dielectric layer in between for insulation. The second termination region has a ring-shaped first source trench structure including a source electrode filling in a source trench with a source dielectric layer in between for insulation.

A semiconductor device is provided. In the semiconductor device, on the upper surface of the semiconductor device, a first horizontal virtual line, a second horizontal virtual line, a third horizontal virtual line, and a fourth horizontal virtual line which extend in parallel with one another along a first axial direction may be defined, and on the upper surface of the semiconductor device, a first vertical virtual line, a second vertical virtual line, and a third vertical virtual line which extend in parallel with one another along a second axial direction perpendicular to the first axial direction may be defined, and the semiconductor device may include a trench region, a gate contact region, and a source contact region, and the trench region may be formed so as to extend in the second axial direction along the first vertical virtual line, extend along the first axial direction from the intersection of the first vertical virtual line and the first horizontal virtual line, extend along the second axial direction from the intersection of the first horizontal virtual line and the second vertical virtual line, and extend along the first axial direction from the intersection of the second vertical virtual line and the second horizontal virtual line, and on the trench region, a plurality of gate polysilicon contact holes and a plurality of shielded polysilicon contact holes may be formed.

A method includes providing a plurality of semiconductor devices on a semiconductor structure, providing a top side metallization on a first side of the semiconductor structure, wherein the top side metallization comprises a plurality of bond pads on each of the semiconductor devices, and providing a back side metallization on a second side of the semiconductor structure opposite the first side of the semiconductor structure. The back side metallization is not provided on portions of the second side of the semiconductor structure corresponding to dicing streets between the semiconductor devices.