The present disclosure relates to a solar cell, a sliced cell and a manufacturing method thereof, a photovoltaic module, and a photovoltaic system. The solar cell includes a substrate, a doped conductive layer, a first passivation film layer, and a first dielectric layer; the doped conductive layer being arranged on a first surface of the substrate; the first passivation film layer and the first dielectric layer being sequentially stacked on a side of the doped conductive layer facing away from the substrate; and the doped conductive layer, the first passivation film layer, and the first dielectric layer all covering the first surface of the substrate; wherein the substrate further includes a plurality of first side surfaces adjacent to the first surface, and the first passivation film layer further covers at least part of surfaces of the plurality of first side surfaces. The solar cell, the photovoltaic module, and the photovoltaic system in the present disclosure can reduce recombination losses at side edges of the solar cell and improve efficiency.

A solar cell, a method for preparing the same and an electrical device are provided. The method for preparing the solar cell includes following steps: providing a substrate, which includes a first surface and a second surface opposite to the first surface; forming a protective material layer on the first surface, and removing part of the protective material layer on a preset first doped region to prepare a protective layer; performing a first doping process in the preset first doped region on the substrate to prepare a substrate including a first doped region. A width of the first doped region is in a range of 10 m to 35 m.

A solar cell according to an embodiment of the present disclosure includes a first passivation layer including a first aluminum oxide layer positioned on a first conductivity-type region composed of a polycrystalline silicon layer having an n-type conductivity and having hydrogen, and a first dielectric layer positioned on the first aluminum oxide layer and including a material different from the first aluminum oxide layer.

The solar cell includes a substrate having electrode regions and non-electrode regions defined alternatively, where a surface of the electrode regions has a first surface structure, a surface of the non-electrode regions has a second surface structure, the first surface structure has a smaller roughness than the second surface structure, and the second surface structure includes multiple first protrusion structures. The solar cell further includes a tunneling dielectric layer, and a first doped conductive layer arranged on the tunneling dielectric layer. The solar cell further includes a passivation layer arranged on the non-electrode regions and the first doped conductive layer and a first electrode arranged in the electrode regions. The first electrode penetrates the passivation layer to be in electrical contact with the first doped conductive layer.

Methods of fabricating solar cells using UV-curing of light-receiving surfaces of the solar cells, and the resulting solar cells, are described herein. In an example, a method of fabricating a solar cell includes forming a passivating dielectric layer on a light-receiving surface of a silicon substrate. The method also includes forming an anti-reflective coating (ARC) layer below the passivating dielectric layer. The method also includes exposing the ARC layer to ultra-violet (UV) radiation. The method also includes, subsequent to exposing the ARC layer to ultra-violet (UV) radiation, thermally annealing the ARC layer.

A low cost IC solution is disclosed to provide Super CMOS microelectronics macros. Hereinafter, the Super CMOS or Schottky CMOS all refer to SCMOS. The SCMOS device solutions with a niche circuit element, the complementary low threshold Schottky barrier diode pairs (SBD) made by selected metal barrier contacts (Co/Ti) to P- and NSi beds of the CMOS transistors. A DTL like new circuit topology and designed wide contents of broad product libraries, which used the integrated SBD and transistors (BJT, CMOS, and Flash versions) as basic components. The macros include diodes that are selectively attached to the diffusion bed of the transistors, configuring them to form generic logic gates, memory cores, and analog functional blocks from simple to the complicated, from discrete components to all grades of VLSI chips. Solar photon voltaic electricity conversion and bio-lab-on-a-chip are two newly extended fields of the SCMOS IC applications.

A solar cell comprises a silicon substrate including a first surface and a second surface opposite to each other; a first doped layer disposed on the first surface; a second doped layer disposed on the second surface, a doped type of the first doped layer is opposite to a doped type of the second doped layer; a first electrode connecting to the first doped layer; a second electrode connecting to the second doped layer; and an isolation trench penetrating the first doped layer along a thickness direction of the silicon substrate and surrounding the first electrode.

The present disclosure relates to the field of solar cell technologies. The present disclosure provides a solar cell and a manufacturing method therefor, a photovoltaic module, and a photovoltaic system. The solar cell includes: a substrate; a tunnel oxide layer stacked on a surface of the substrate, the tunnel oxide layer being an oxide layer including at least a silicon element and an oxygen element; and a polysilicon doped conductive layer stacked on a side of the tunnel oxide layer facing away from the substrate. The tunnel oxide layer is doped with a carbon element and a hydrogen element.

The invention provides a method for increasing the usable surface area of a semiconductor wafer having a substantially planar surface and a thickness dimension at right angles to said substantially planar surface, the method including the steps of selecting a strip thickness for division of the wafer into a plurality of strips, selecting a technique for cutting the wafer into the strips at an angle to the substantially planar surface, in which the combined strip thickness and width of wafer removed by the cutting is less than the thickness of the wafer, cutting the wafer into strips using the selected technique and separating the strips from each other.

A fabrication method of a solar cell, the method includes doping a silicon substrate having a first conductive type impurity with a second conductive type impurity, the second conductive type impurity being opposite to the first conductive type impurity, and thereby forming an emitter layer at a front surface part of the silicon substrate, forming an antireflection film on the emitter layer, forming a front electrode on the antireflection film, forming a rear electrode on a rear surface of the silicon substrate, and forming a back surface field layer at a rear surface part of the silicon substrate, the back surface field layer having a concentration of the first conductive type impurity that is higher than that of the silicon substrate, the back surface field layer having a different concentration of the second conductive type impurity from that of the emitter layer.