A method for forming a poly-insulator-poly (PIP) capacitor is disclosed. A semiconductor substrate having a capacitor forming region is provided. A first capacitor dielectric layer is formed on the capacitor forming region. A first poly electrode is formed on the first capacitor dielectric layer. A second capacitor dielectric layer is formed on the first poly electrode. A second poly electrode is formed on the second capacitor dielectric layer. A third poly electrode is formed adjacent to a first sidewall of the second poly electrode. A third capacitor dielectric layer is formed between the third poly electrode and the second poly electrode. A fourth poly electrode is formed adjacent to a second sidewall of the second poly electrode that is opposite to the first sidewall. A fourth capacitor dielectric layer is formed between the fourth poly electrode and the second poly electrode.

Provided are a thin film structure, a capacitor including the thin film structure, a semiconductor device including the thin film structure, and a method of manufacturing the thin film structure, in which the thin film structure may include: a first electrode thin film disposed on a substrate and including a first perovskite-based oxide; and a protective film disposed on the first electrode thin film and including a second perovskite-based oxide that is oxygen-deficient and includes a doping element. The thin film structure may prevent the deterioration of conductivity and a crystalline structure of a perovskite-based oxide electrode, which is a lower electrode, even in a high-temperature oxidizing atmosphere for subsequent dielectric film deposition.

A semiconductor device according to an embodiment of the present disclosure includes a substrate, a first epitaxial electrode layer disposed on the substrate, a ferroelectric epitaxial layer disposed on the first epitaxial electrode layer, a dielectric epitaxial layer disposed on the ferroelectric epitaxial layer, and a second epitaxial electrode layer disposed on the dielectric epitaxial layer. The ferroelectric epitaxial layer implements a negative capacitance. Each of the first and second epitaxial electrode layers includes conductive pyrochlore oxide. The ferroelectric epitaxial layer and the dielectric epitaxial layer are electrically connected in series is non-ferroelectric. A dielectric structure comprising the ferroelectric epitaxial layer and the dielectric epitaxial layer is non-ferroelectric.

A device structure comprises a first conductive interconnect, an electrode structure on the first conductive interconnect, an etch stop layer laterally surrounding the electrode structure; a plurality of memory devices above the electrode structure, where individual ones of the plurality of memory devices comprise a dielectric layer comprising a perovskite material. The device structure further comprises a plate electrode coupled between the plurality of memory devices and the electrode structure, where the plate electrode is in direct contact with a respective lower most conductive layer of the individual ones of the plurality of memory devices. The device structure further includes an insulative hydrogen barrier layer on at least a sidewall of the individual ones of the plurality of memory devices; and a plurality of via electrodes, wherein individual ones of the plurality of via electrodes are on a respective one of the individual ones of the plurality of memory devices.

An integrated circuit device includes a capacitor structure, wherein the capacitor structure includes: a bottom electrode over a substrate; a supporter on a sidewall of the bottom electrode; a dielectric layer on the bottom electrode and the supporter; and a top electrode on the dielectric layer and covering the bottom electrode. The bottom electrode comprises: a base electrode layer over the substrate and extending in a first direction that is perpendicular to a top surface of the substrate, and a conductive capping layer including niobium nitride that is between a sidewall of the base electrode layer and the dielectric layer, and also between a top surface of the base electrode layer and the dielectric layer.

An apparatus and configuring scheme where a capacitive input circuit can be programmed to perform different logic functions by adjusting the switching threshold of the capacitive input circuit. Digital inputs are received by respective capacitors on first terminals of those capacitors. The second terminals of the capacitors are connected to a summing node. A pull-up and pull-down device are coupled to the summing node. The pull-up and pull-down devices are controlled separately. During a reset phase, the pull-up and/or pull-down devices are turned on or off in a sequence, and inputs to the capacitors are set to condition the voltage on node n1. As such, a threshold for the capacitive input circuit is set. After the reset phase, an evaluation phase follows. In the evaluation phase, the output of the capacitive input circuit is determined based on the inputs and the logic function configured during the reset phase.

In accordance with some embodiments of the present disclosure, a memory device is provided. The memory device may include a first electrode, a ferroelectric layer fabricated on the first electrode, and a second electrode fabricated on the ferroelectric layer. The ferroelectric layer includes a plurality of ferroelectric films and a plurality of interface layers stacked alternately. Each of the ferroelectric films comprises at least one ferroelectric material, such as hafnium oxide (HfO.sub.2), zirconium oxide (ZrO.sub.2), zirconium-doped hafnium oxide (Hf.sub.1-xZr.sub.xO.sub.2), scandium-doped aluminum nitride (Al.sub.1-xSc.sub.xN), titanates (BaTiO.sub.3), niobates (LiNbO.sub.3), tantalates (NaTaO.sub.3), etc. Each of the interface layers comprises at least one dielectric material that is more chemically stable than the ferroelectric material, such as aluminum oxide.

An integrated circuit device includes a transistor on a substrate, and a capacitor structure connected to the transistor, where the capacitor includes a first electrode, a dielectric layer structure on the first electrode and in which a plurality of dielectric layers are stacked, and a second electrode on the dielectric layer structure, and where the plurality of dielectric layers include a first dielectric layer including a ferroelectric material in a rhombohedral crystal phase, and a second dielectric layer in a crystal phase different from the rhombohedral crystal phase of the first dielectric layer.

A capacitor includes a first electrode including a first reinforcement material having a perovskite crystal structure; and a first metallic material having a perovskite crystal structure; a second electrode on the first electrode; and a dielectric layer between the first electrode and the second electrode, wherein the first metallic material has greater a greater electronegativity than that of the first reinforcement material.

A calabash-shaped MIM capacitor structure includes a stacked layer. The stacked layer includes numerous dielectric layers. An MIM capacitor is disposed within the stacked layer. The MIM capacitor includes a calabash-shaped profile. The calabash-shaped profile includes a rounded bottom, a narrow body and a rounded shoulder disposed from bottom to top.