In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a bottom electrode disposed over a substrate and a top electrode disposed over the bottom electrode. A ferroelectric switching layer and a first seed layer are arranged between the bottom electrode and the top electrode. A second seed layer continuously extends between a lower surface physically contacting the ferroelectric switching layer and an upper surface physically contacting the top electrode. The first seed layer, the second seed layer, and the ferroelectric switching layer include non-monoclinic crystal phases.

Semiconductor structures and methods are provided. An exemplary method includes depositing forming a first metal-insulator-metal (MIM) capacitor over a substrate and forming a second MIM capacitor over the first MIM capacitor. The forming of the first MIM capacitor includes forming a first conductor plate over a substrate, the first conductor plate comprising a first metal element, conformally depositing a first dielectric layer on the first conductor plate, the first dielectric layer comprising the first metal element, forming a first high-K dielectric layer on the first dielectric layer, conformally depositing a second dielectric layer on the first high-K dielectric layer, the second dielectric layer comprising a second metal element, and forming a second conductor plate over the second dielectric layer, the second conductor plate comprises the second metal element.

A capacitor includes a lower electrode, an upper electrode, a dielectric film between the lower electrode and the upper electrode, and a leakage current reduction film between the upper electrode and the dielectric film. The leakage current reduction film includes a doped AlZrO film, wherein an ionic radius of a dopant contained in the doped AlZrO film is greater than or equal to about 130 picometers (pm).

A semiconductor device includes a substrate, lower electrodes on the substrate, a dielectric layer covering the lower electrodes, and an upper electrode covering the dielectric layer. The dielectric layer includes a first region in contact with the lower electrodes, a second region in contact with the upper electrode, and a third region between the first and second regions. The third region includes a first insertion layer including a first oxide including a first metal having a first valence and a second oxide including a second metal having a second valence different from the first valence. A thickness of the dielectric layer is about 40 to about 60 . A thickness of the first insertion layer is about 3 to about 10 . A ratio of the second metal to total elements in the dielectric layer is about 5 at % to about 15 at %.

A ferroelectric device (100) that includes a metal nitride film (130) with favorable ferroelectricity is provided. The ferroelectric device comprises a first conductor (110), a metal nitride film over the first conductor, a second conductor (120) over the metal nitride film, a first insulator (155) over the second conductor, and a second insulator (152) over the first insulator. The first insulator includes regions in contact with the side surface of the metal nitride film and the side surface and the top surface of the second conductor; the metal nitride film has ferroelectricity; the metal nitride film contains a first element, a second element, and nitrogen; the first element is one or more elements selected from Group 13 elements; the second element is one or more elements selected from Group 2 elements to Group 6 elements and Group 13 elements other than the first element; the first conductor and the second conductor each contain nitrogen; the first insulator contains aluminum and oxygen; and the second insulator contains silicon and nitrogen.

A preparation method for the capacitor structure includes: forming a dielectric layer on a first electrode, wherein, the dielectric layer includes a first amorphous layer and a high dielectric constant layer which are stacked, the first amorphous layer maintaining an amorphous structure after annealing, and the high dielectric constant layer being formed by crystallizing an initial dielectric constant layer after annealing; and forming a second electrode on the dielectric layer. Since the first amorphous layer remains an amorphous structure after annealing, electron transport can be suppressed, thereby reducing the leakage current of the capacitor structure.

A memory device, transistor, and methods of making the same, the memory device including a memory cell including: a bottom electrode layer; a high-k dielectric layer disposed on the bottom electrode layer; a discontinuous seed structure comprising discrete particles of a metal disposed on the high-k dielectric layer; a ferroelectric (FE) layer disposed on the seed structure and directly contacting portions of high-k dielectric layer exposed through the seed structure; and a top electrode layer disposed on the FE layer.

A semiconductor structure may be located over a substrate, and may include a parallel connection of a first component and a second component. The first component includes a series connection of a diode and a capacitor that is selected from a metal-ferroelectric-metal capacitor and a metal-antiferroelectric-metal capacitor. The second component includes a battery structure. The semiconductor structure may be used as a combination of an energy harvesting device and an energy storage structure that utilizes heat from adjacent semiconductor devices or from other heat sources.

The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor which in turn comprises a polar layer comprising a base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor stack additionally comprises first and second crystalline conductive oxide electrodes on opposing sides of the polar layer. The capacitor stack further comprises first and second barrier metal layers on respective ones of the first and second crystalline conductive oxide electrodes on opposing sides of the polar layer.

A metal-insulator-metal capacitor includes a bottom electrode, a dielectric layer, a superlattice layer, a silicon dioxide layer and a top electrode stacked from bottom to top. The superlattice layer contacts the dielectric layer. A silicon dioxide layer has a negative voltage coefficient of capacitance.