A compound semiconductor stacked structure is constituted by including: a buffer layer; an n-type conductive region that is formed at one portion of the buffer layer; an channel layer that is formed on a top surface of the buffer layer and on a top surface of the n-type conductive region; and an barrier layer that is formed above the channel layer and contains In.sub.x1Al.sub.y1Ga.sub.z1N (0x1<1, and 0<y1<1, and 0z1<1, and x1+z1>0, and x1+y1+z1=1); and includes electrodes that are formed on the n-type conductive region.

A semiconductor device includes a substrate, a first semiconductor layer formed over the substrate, a plurality of contact layers formed over portions of the first semiconductor layer, a second semiconductor layer formed over another portion of the first semiconductor layer and on side surfaces of the contact layers, a source electrode formed on one of the contact layers, a drain electrode formed on another one of the contact layers, and a gate electrode formed on the second semiconductor layer. The first semiconductor layer is formed of a material including GaN, the second semiconductor layer is formed of In.sub.x1Al.sub.y1Ga.sub.1-x1-y1N (0<x10.2, 0<y1<1), and the contact layers are formed of a material including GaN.

A compound semiconductor stacked structure is constituted by including: a buffer layer; an n-type conductive region that is formed at one portion of the buffer layer; an channel layer that is formed on a top surface of the buffer layer and on a top surface of the n-type conductive region; and an barrier layer that is formed above the channel layer and contains In.sub.x1Al.sub.y1Ga.sub.z1N (0x1<1, and 0<y1<1, and 0z1<1, and x1+z1>0, and x1+y1+z1=1); and includes electrodes that are formed on the n- type conductive region.

A semiconductor device includes a carrier transit layer including a first region and second and third regions having a density of a donor impurity element higher than that of the first region, an In.sub.XAl.sub.YGa.sub.(1-X-Y)N (0<X<1, 0<Y<1, 0<X+Y1) carrier supply layer provided over the carrier transit layer and having a density of a donor impurity element lower than that of the second and third regions, a source electrode provided over the second region, a drain electrode provided over the third region, and a gate electrode provided over the carrier supply layer between the source electrode and the drain electrode.

A junction field effect transistor (JFET) comprises an insulating carrier substrate, a base semiconductor substrate formed on the insulating carrier substrate and a gate region formed on the base semiconductor substrate. The gate region forms a junction with the base semiconductor substrate. The JFET further comprises a first source/drain region formed on the base semiconductor substrate and located on a first side of the gate region and a second source/drain region formed on the base semiconductor substrate and located on a second side of the gate region. A gate stack is deposited on the gate region, a first source/drain stack is deposited on the first source/drain region and a second source/drain stack is deposited on the second source/drain region. At least one of the gate stack, first source/drain stack and second source/drain stack overlaps onto another one of the gate stack, first source/drain stack and second source/drain stack.

A process of forming a semiconductor device type of high electron-mobility transistor (HEMT) made of nitride semiconductor materials, and a HEMT formed thereby are disclosed. The process includes steps of implanting impurities into regions corresponding to n+ regions, activating the impurities by annealing, removing a disarranged region between the n+ regions, and forming the gate electrode onto the region where the disarranged region is removed in advance to the formation. The annealing, even when an insulating film covers the surface, causes the disarranged region primarily due to the sublimation of nitrogen (N). When the gate electrode is formed on the disarranged region, leak currents between the electrodes become substantial. Contrary, the HEMT of the invention provides the gate electrode onto a surface where the disarranged region is removed.

A JFET is formed with vertical and horizontal elements made from a high band-gap semiconductor material such as silicon carbide via triple implantation of a substrate comprising an upper drift region and a lower drain region, the triple implantation forming a lower gate, a horizontal channel, and an upper gate, in a portion of the drift region. A source region may be formed through a portion of the top gate, and the top and bottom gates are connected. A vertical channel region is formed adjacent to the planar JFET region and extending through the top gate, horizontal channel, and bottom gate to connect to the drift, such that the lower gate modulates the vertical channel as well as the horizontal channel, and current from the sources flows first through the horizontal channel and then through the vertical channel into the drift.

A JFET is formed with vertical and horizontal elements made from a high band-gap semiconductor material such as silicon carbide via triple implantation of a substrate comprising an upper drift region and a lower drain region, the triple implantation forming a lower gate, a horizontal channel, and an upper gate, in a portion of the drift region. A source region may be formed through a portion of the top gate, and the top and bottom gates are connected. A vertical channel region is formed adjacent to the planar JFET region and extending through the top gate, horizontal channel, and bottom gate to connect to the drift, such that the lower gate modulates the vertical channel as well as the horizontal channel, and current from the sources flows first through the horizontal channel and then through the vertical channel into the drift.

A process of forming a nitride semiconductor device is disclosed. The process includes steps of (a) implanting impurities into a portion of nitride semiconductor layers epitaxially grown on a substrate; (b) forming a silicon nitride (SiN) film on the nitride semiconductor layers; and (c) annealing the nitride semiconductor layers for activating the implanted impurities as covering the nitride semiconductor layers by the SiN film. The process has a feature that the SiN film shows, in a Fourier Transformation Infrared (FT-IR) spectroscopy measured before the step of annealing, absorbance peaks attributed to translational motions of a SiH bond and an NH bond at most 1/30 of an absorbance peak attributed to a SiN bond.

Circuits and devices for bidirectional normally-off switches are described. A circuit for a bidirectional normally-off switch includes a depletion mode transistor and an enhancement mode transistor. The depletion mode transistor includes a first source/drain node, a second source/drain node, a first gate, and a second gate. The enhancement mode transistor includes a third source/drain node and a fourth source/drain node, and a third gate. The third source/drain node is coupled to the first source/drain node.