A semiconductor structure and a method of fabricating thereof including a substrate having a device region and a dummy region. The device region includes a number of N-type device cells having a plurality of operational N-type transistors and a number of P-type device cells having a plurality of operational P-type transistors. The dummy region includes a number of N-type dummy cells having a plurality of non-operational N-type transistors and a number of P-type dummy cells having a plurality of non-operational P-type transistors, and a total number of the N-type device cells and P-type device cells is equal to a total number of the N-type dummy cells and P-type dummy cells.

Provided is a multi-stack semiconductor device including a back-side wiring layer having a first back-side line and a second back-side line each extending in a first horizontal direction, a first FET on the back-side wiring layer and including a lower source/drain region, a second FET on the first FET and including an upper source/drain region, and a hybrid tap cell having a first tap cell and a second tap cell that are adjacent to each other in a second horizontal direction perpendicular to the first horizontal direction, wherein the first tap cell includes a first through structure electrically connected to the first back-side line, and the second tap cell comprises a second through structure extending through an upper dummy source/drain region and electrically connected to the second back-side line, where the upper dummy source/drain region is spaced apart from the upper source/drain region in the first horizontal direction.

A semiconductor device includes a first source/drain, a second source/drain, a first nanosheet, a second nanosheet, and interconnect, which is configured to electrically connect the first source/drain to the second source/drain, and contacts the first and second nanosheets. The interconnect includes an enclosure, a first side via region extending inside the enclosure and electrically connected to the first source/drain, a second side via region extending inside the enclosure and electrically connected to the second source/drain, and a side metal region, which extends inside the enclosure and is electrically connected to the first side via region and the second side via region.

A semiconductor device may include a first active pattern on a substrate, a pair of first source/drain patterns on the first active pattern and a first channel pattern between the first source/drain patterns, the first channel pattern including first semiconductor patterns, which are spaced apart from each other in a stacked formation, a gate electrode on the first channel pattern, a first gate cutting pattern adjacent to the first channel pattern that penetrates the gate electrode, and a first spacer pattern between the first gate cutting pattern and the first channel pattern. The first spacer pattern may include a first remaining pattern adjacent to an outermost side surface of at least one of the first semiconductor patterns and a second remaining pattern on the first remaining pattern. The second remaining pattern may be spaced apart from the first gate cutting pattern.

A three-dimensional semiconductor device is provided. The three-dimensional semiconductor device may include a first active region on a substrate, the first active region including a lower channel pattern and lower source/drain patterns connected to the lower channel pattern, a second active region on the first active region, the second active region including an upper channel pattern and an upper source/drain pattern connected to the upper channel pattern, a gate electrode on the lower channel pattern and the upper channel pattern, and a gate cutting pattern penetrating the gate electrode, and the gate cutting pattern may have a middle width between an upper surface and a lower surface thereof that is less than an upper width of an upper portion of the gate cutting pattern and a lower width of a lower portion of the gate cutting pattern.

A semiconductor structure includes a first transistor, a second transistor, a gate structure, and a first source/drain contact. The first transistor includes first nanostructures stacked from each other in a Z-direction, and a first source/drain feature and a second source/drain feature on opposite sides of the first nanostructures in an X-direction. The second transistor is arranged with the first transistor in a Y-direction. The second transistor includes second nanostructures stacked from each other in the Z-direction, and a third source/drain feature and a fourth source/drain feature on opposite sides of the second nanostructures in the X-direction. The gate structure extends in the Y-direction and wraps around the first nanostructures and the second nanostructures. The first source/drain contact extends in the Y-direction and is under and electrically connected to the second source/drain feature and the fourth source/drain feature.

A method includes forming a first semiconductor layer and a second semiconductor layer vertically above the first semiconductor layer over a substrate; forming a first ferroelectric layer and a second ferroelectric layer wrapping around the first semiconductor layer and the second semiconductor layer, respectively; forming a first gate structure and a second gate structure over the first ferroelectric layer and the second ferroelectric layer, respectively, wherein the first gate structure is in contact with the second gate structure; and forming a conductive feature electrically connecting a drain region of the first semiconductor layer with a drain region of the second semiconductor layer.

There is provided a logic gate comprising a semiconductor device. The semiconductor device includes a charge reservoir layer disposed between a first charge accepting layer and a second charge accepting layer. The first charge accepting layer defines a first current flow path that is connected to a common output contact at one end and a drive contact at the other end. The second charge accepting layer defines a current flow path that is connected to the common output contact at one end and a ground contact at the other end. The charge reservoir layer comprises a potential well having a lowest energy state for mobile charge carriers that is at a lower energy than the lowest energy state for mobile charge carriers of both the first and second charge accepting layers. The logic gate further comprises a control gate and a ground electrode that are separated from the charge accepting layers by non-conducting layers. The control gate and the ground electrode are configured to apply an input voltage across the semiconductor device, such that mobile charge carriers confined within the charge reservoir layer are transferred to the first charge accepting layer at a first applied input voltage and transferred to the second charge accepting layer at a second applied input voltage.

An integrated circuit (IC) device includes a first metallization layer, a second metallization layer, and a transistor layer between the first and second metallization layers. The transistor layer includes a first gate structure and a second gate structure. A conductive via between the first gate structure and the second gate structure extends through the first metallization layer and extends at least partially into the second metallization layer.

A semiconductor structure is provided. The semiconductor structure includes a plurality of transistors formed in an active region of a device layer, a first power line disposed on a front side of the device layer and extending in a first direction, a first connecting feature disposed on a source/drain region of the transistors and extending in a second direction perpendicular to the first direction, a second power line disposed on a back side of the device layer and extending in the first direction, and a feedthrough via formed on and in contact with the second power line. The active region extending in the first direction and the feedthrough via are disposed on two opposite sides of the first power line from a top view. The second power line is electrically connected to the source/drain region of the transistors through the feedthrough via and the first connecting feature.