A semiconductor device includes a buffer layer formed with a semiconductor adapted to produce piezoelectric polarization, and a channel layer stacked on the buffer layer, wherein a two-dimensional hole gas, generated in the channel layer by piezoelectric polarization of the buffer layer, is used as a carrier of the channel layer. On a complementary semiconductor device, the semiconductor device described above and an n-type field effect transistor are formed on the same compound semiconductor substrate. Also, a level shift circuit is manufactured by using the semiconductor device. Further, a semiconductor device manufacturing method includes forming a compound semiconductor base portion, forming a buffer layer on the base portion, forming a channel layer on the buffer layer, forming a gate on the channel layer, and forming a drain and source with the gate therebetween on the channel layer.

Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer made of a first III-nitride material to act as a channel region of the e-HEMT, and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and made of a second III-nitride material to act as a barrier layer. Source and drain regions are arranged over the ternary III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.

A semiconductor may include a semiconductor substrate including a first region and a second region disposed at opposite sides of the first region, a first trench formed in the first region, a buffer layer filling a portion of the first trench, a first semiconductor layer formed on the buffer layer, a second semiconductor layer forming a hetero-junction with the first semiconductor layer on the first semiconductor layer of the first region and a gate electrode formed on the second semiconductor layer of the first region.

A nitride semiconductor device includes: a substrate; a buffer layer formed on the substrate; a laminated body formed by two or more cycles of semiconductor layers each including a first nitride semiconductor layer, and a second nitride semiconductor layer having a larger band gap than a band gap of the first nitride semiconductor layer, the first and second nitride semiconductor layers being laminated in this order on the buffer layer; a first electrode; and a second electrode. A channel layer is formed in each of the semiconductor layers at an interface between the first nitride semiconductor layer and the second nitride semiconductor layer. A carrier concentration of the channel layer in the uppermost semiconductor layer is lower than a carrier concentration of each of the channel layers of the other semiconductor layers.

A semiconductor device includes a first nitride semiconductor layer formed over a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer, a third nitride semiconductor layer formed over the second nitride semiconductor layer, a fourth nitride semiconductor layer formed over the third nitride semiconductor layer, a trench that penetrates the fourth nitride semiconductor layer and reaches as far as the third nitride semiconductor layer, a gate electrode disposed by way of a gate insulation film in the trench, a first electrode and a second electrode formed respectively over the fourth nitride semiconductor layer on both sides of the gate electrode, and a coupling portion for coupling the first electrode and the first nitride semiconductor layer.

A nitride semiconductor device includes a conductive substrate and a nitride semiconductor layer. The nitride semiconductor layer is disposed on the conductive substrate. The nitride semiconductor layer includes a first transistor structure of a lateral type and a second transistor structure of a lateral type. The conductive substrate includes a first potential control region and a second potential control region capable of controlling potential independently from the first potential control region. In planar view of the nitride semiconductor layer, the first transistor structure overlaps the first potential control region and the second transistor structure overlaps the second potential control region.

A semiconductor device includes an active layer, a source electrode, a drain electrode, a gate electrode, a first insulating layer, a first source pad, and a first drain pad. The source electrode, the drain electrode, and the gate electrode are disposed, on an active region of the active layer. The first insulating layer is disposed on the source electrode, the drain electrode, and the gate electrode. The first source pad and the first drain pad are disposed on the first insulating layer and the active region. The first source pad includes a first source body and a first source branch. The first source branch is electrically connected to the first source body and disposed on the source electrode. The first drain pad includes a first drain body and a first drain branch. The first drain branch is electrically connected to the first drain body and disposed on the drain electrode.

An HEMT with a stair-like compound layer as a drain includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A source electrode, a gate electrode and a drain electrode are disposed on the second III-V compound layer. The gate electrode is disposed between the source electrode and the drain electrode. A first P-type III-V compound layer is disposed between the drain electrode and the second III-V compound layer. The first P-type III-V compound layer is stair-like.

A semiconductor device includes a barrier region and a channel region, source and drain electrodes, and a gate structure that is configured to control a conductive connection between the source and drain electrodes, wherein the barrier region comprises a first barrier layer, a second barrier layer, and a third barrier layer, wherein in a central portion of the device the second barrier layer and the third barrier layer are disposed over the channel region, wherein in outer lateral portions of the device the first barrier layer is disposed over the channel region, and wherein a molar fraction of a second type III element in the central portion is higher than a molar fraction of the second type III element in the first barrier layer.

A semiconductor device includes: a substrate; a first nitride semiconductor layer on the substrate; a second nitride semiconductor layer on the first nitride semiconductor layer; a drain contact and a source contact on the second nitride semiconductor layer; a common contact on the second nitride semiconductor layer and between the drain contact and source contact; a first gate structure on the second nitride semiconductor layer and between the drain contact and common contact; a second gate structure on the second nitride semiconductor layer and between the common contact and source contact; a conductive wire on the source contact; a dielectric layer on the second nitride semiconductor layer and covering a portion of a lateral surface of the conductive wire; and a conductive via connected to the conductive wire, extending through a portion of the dielectric layer, the second nitride semiconductor layer, and the first nitride semiconductor layer to the substrate.