A semiconductor diode includes a wide bandgap semiconductor body having opposing first and second surfaces. The wide band gap semiconductor body includes a first pn junction diode having a first p-doped region adjoining the first surface and a first n-doped region adjoining both surfaces. The semiconductor diode further includes a semiconductor element including a second pn junction diode having a second p-doped region and second n-doped region, and a dielectric structure between the wide bandgap semiconductor body and semiconductor element. The dielectric structure electrically insulates the wide bandgap semiconductor body from the semiconductor element. The bandgap energy of the semiconductor element is smaller than that of the wide bandgap semiconductor body. A cathode contact is electrically connected to the first n-doped region at the second surface. The second n-doped region of the second pn junction diode is electrically coupled to the first n-doped region of the first pn junction diode.

In a metal-oxide-semiconductor chip device first and second source structures are provided on a first side of the semiconductor substrate as a pair. The drain structure is provided on a second side of the semiconductor substrate. The second side faces away from the first source structure and the second source structure. A first channel structure is provided between and separates the first source structure and the semiconductor substrate. A second channel structure is provided between and separates the second source structure and the semiconductor substrate. A gate structure is provided on the first side of the semiconductor substrate. The first and second channel structures are configured as mirror images of each other, and a wide-width area and a narrow-width area are formed between the first and second channel structures as a result of varied spacing between the first and second channel structures.

A junction field-effect transistor with asymmetric gates, and a method of making the same. A channel is constructed of semiconductor material, a source is located at a first end of the channel, and a drain is located at a second end. A first gate is located at and extends along a first side of the channel and creates a first depletion region, and a second gate is located at and extends along a second side of the channel and creates a second depletion region. The gates are physically asymmetric with regard to at least one of their relative position along the channel, their relative size, or their relative shape (e.g., one gate may project into the channel toward the other gate). The physical asymmetry of the first and second gates results in their respective depletion regions being asymmetric, which affects the ability to control electrical current flowing through the channel.

A field-effect transistor with a shielded source, and a method of making the same. A volume of semiconductor material includes first and second vertically spaced ends and first and second laterally spaced sides. First and second laterally spaced gates are provided in the volume of semiconductor material. A source is located at the first end between the first and second gates, a drain is provided, and a channel extends therebetween. The first gate includes a lower first gate portion spaced below and extending beneath the source so as to create a turn in the channel around the lower first gate portion.

The planar junction field-effect transistor provides enhanced channel control. A method of making such a JFET is also disclosed. A volume of semiconductor material includes a first end and a second end, a source and a first gate are located at the first end, a drain is spaced apart from the source, and a channel is provided between the source and the drain. A second gate is located between the source and drain so as to be surrounded, or buried, in a first dimension and a second dimension by the semiconductor material, and thereby divides the channel into multiple non-linear channel paths. The gates cooperatively determine the channel paths and enhance the channel control. The second gate may include an extension in a third dimension through the semiconductor material. The extension may present an exposed surface for an electrical terminal for receiving a voltage.

A mesa junction field-effect transistor is provided with channel engineering, and a method of making such a device is disclosed. A volume of semiconductor material includes a first end, a second end, a first side, and a second side. A channel extends between a source located at the first end and a drain. A first gate is located at the first side. A second gate is located at the second side, opposite the first gate, and includes upper and lower components located along an opposite side of the channel. The lower second gate component is spaced below and extends beneath the source, thereby creating at least two turns in the channel. The first and second gates cooperate to provide multiple control points in the non-linear channel for controlling electrical current flowing through the channel.

A trench junction field effect transistor (trench JFET) includes a mesa region confined by first and second trenches along a first lateral direction. The first and second trenches extend into a semiconductor body from a first surface of the semiconductor body. A mesa channel region of a first conductivity type is confined, along the first lateral direction, by first and second gate regions of a second conductivity type. A first pn junction is defined by the mesa channel region and the first gate region. A second pn junction is defined by the mesa channel region and the second gate region. The mesa channel region includes, along the first lateral direction, first, second and third mesa channel sub-regions having a same extent along the first lateral direction.

A semiconductor device includes a junction field effect transistor (JFET) including a source electrode, a drain electrode, and a gate electrode, and a metal oxide semiconductor field effect transistor (MOSFET) including a source electrode, a drain electrode, and a gate electrode. The JFET and the MOSFET are cascode-connected such that the source electrode of the JFET and the drain electrode of the MOSFET are electrically connected. A gate voltage dependency of the JFET or a capacitance ratio of a mirror capacitance of the MOSFET to an input capacitance of the MOSFET is adjusted in a predetermined range.

A semiconductor device includes: a semiconductor body with an edge region arranged between an inner region and an edge surface; a first semiconductor region of a first doping type in the inner region; and a second semiconductor region of a second doping type in the inner and edge regions. An edge termination structure includes: a third semiconductor region in the edge region adjoining the first semiconductor region; a surface section of the second semiconductor region adjoining a first main surface of the semiconductor body; and an amorphous passivation layer having a specific resistance higher than 10.sup.9 cm adjoining the third semiconductor region and the surface section. An electrically active doping dose of the third region at a lateral position spaced apart from the first region by 50% of a width of the edge termination structure is at least Q.sub.BR/q, wherein Q.sub.BR is breakdown charge and q is elementary charge.

A method includes providing a two-level gallium nitride (GaN) epitaxial substrate comprising a first GaN drift layer characterized by a first doping concentration and a second GaN drift layer disposed on the first GaN drift layer and characterized by a second doping concentration higher than the first doping concentration and forming a plurality of pedestals in the second GaN drift layer. Each of the plurality of pedestals is laterally separated by one of a plurality of funnels. The method also includes performing a channel regrowth process to regrow a plurality of n-type GaN channels, each disposed in one of the plurality of funnels, and performing a gate regrowth process to regrow p-type GaN. The method further includes patterning the p-type GaN to form a plurality of p-type GaN gates disposed in one of the plurality of n-type GaN channels, and forming source contacts, gate contacts, and a drain contact.