A transistor device according to some embodiments includes a channel layer, a barrier layer on the channel layer, and source and drain contacts on the barrier layer, and a gate contact on the barrier layer between the source and drain contacts. The channel layer includes a sub-layer having an increased doping concentration level relative to a remaining portion of the channel layer. The presence of the sub-layer may reduce drain lag without substantially increasing gate lag.

A semiconductor device, according to an embodiment, includes a main transistor, a sub transistor that is connected to one terminal of the main transistor, and a resistive element that is connected between another terminal of the main transistor and the sub transistor. The main transistor includes a main channel layer and a barrier layer, which is positioned on the main channel layer and contains a material having an energy band gap different from that of the main channel layer. The sub transistor includes a first sub drift region having a first 2-dimensional electron gas (2DEG) region. The resistive element includes a channel pattern that is electrically connected between a sensing electrode of the sub transistor and a main source electrode of the main transistor, and the channel pattern includes a second sub drift region having a second 2DEG region.

A transistor device includes a semiconductor structure, source and drain contacts on the semiconductor structure, a gate on the semiconductor structure between the source and drain contacts, and a surface passivation layer on the semiconductor structure between the gate and the source or drain contact. The surface passivation layer includes an opening therein that exposes a first region of the semiconductor structure for processing the first region differently than a second region of the semiconductor structure adjacent the gate. Related devices and fabrication methods are also discussed.

A device and method of fabricating a device having depletion-mode and enhancement-mode high-electron-mobility transistors (HEMTs) on a single wafer are disclosed. The method of fabrication involves providing semiconductor layers capable of sustaining a two-dimensional electron sheet to enable electrical current to flow through the HEMT, forming a series of trenches and fins in the semiconductor layers over an active area of the semiconductor layers on which a gate contact terminal is to be set down, the fins of respective HEMTs having different widths resulting in different voltage thresholds for the respective depletion-mode HEMTs.

Semiconductor structures that inhibit the conductivity of parasitic channels are described. In one example, a semiconductor structure includes a substrate, a III-nitride material region over a top surface of the substrate, a first species implanted within at least one region of surface region of the substrate in a first pattern spatially defined across a lateral dimension of the substrate, and a second species implanted within at least one region of the III-nitride material region. The second species can be implanted in a second pattern spatially defined across the lateral dimension of the substrate. The surface region of the substrate includes a parasitic channel. The at least one region of the substrate in which the first species is implanted includes a low-conductivity parasitic channel or is free of the parasitic channel.

A high electron mobility transistor includes a stack of layers including a passivation layer and a heterojunction including a first semiconductor layer, a second semiconductor layer and a two-dimensional electron gas at the interface thereof, one surface of the passivation layer being in contact with the first semiconductor layer; a source metal contact and/or a drain metal contact and a gate electrode; an n+ doped zone situated inside the heterojunction; the source metal contact and/or the drain metal contact being positioned at the level of a recess formed in the stack of layers, the source metal contact and/or said drain metal contact having a thickness defined by an upper face and a lower face substantially parallel to the plane of the layers, the upper face being planar, the lower face being in contact with the n+ doped zone and below the interface between the first and second semiconductor layers.

Provided is a semiconductor device including an enhancement mode (E-mode) high electron mobility transistor (HEMT). The E-mode HEMT includes a substrate, and a channel layer disposed on the substrate. A barrier structure disposed on the channel layer. A pair of source/drain (S/D) metals respectively disposed on the channel layer at opposite sides of the barrier structure. A gate metal disposed on the barrier structure between the pair of S/D metals. The channel layer has a two-dimensional electron gas (2DEG) layer close to an interface between the channel layer and the barrier structure. A fluorine ion concentration in the channel layer adjacent to the 2DEG layer is greater than that away from the 2DEG layer.

A method (of forming a semiconductor device) includes: forming first, second and third channel-stacks each including interleaved precursor-active layers and first sacrificial layers being plus an isolation boundary layer above which is some but not all of the first sacrificial layers; and each of the channel-stacks being separated from nearest other structures by corresponding first and second recesses; forming first source/drain (S/D) features configured with a first dopant type including: partially filling the first and second recesses of the second channel-stack with a first S/D material; and filling the first and second recesses of the third channel-stack with the first S/D material; and forming second S/D features configured a second dopant type including: further filling the first and second partially-filled recesses of the second channel-stack with a second S/D material; and filling the first and second recesses of the first channel-stack with the second S/D material.

A semiconductor memory device includes a plurality of transistors disposed along a major surface of a substrate, a plurality of metallization layers including a plurality of metal tracks and disposed over the major surface of the substrate, and a plurality of memory cells formed within one or more of the metallization layers. At least one of the plurality of transistors is electrically coupled to the plurality of memory cells. Each of the plurality of memory cells includes an access transistor and a storage capacitor electrically coupled to each other in series and physically arranged with respect to each other along a vertical direction.

Provided is a semiconductor device including an enhancement mode (E-mode) high electron mobility transistor (HEMT). The E-mode HEMT includes a substrate, and a channel layer disposed on the substrate. A barrier structure disposed on the channel layer. A pair of source/drain (S/D) metals respectively disposed on the channel layer at opposite sides of the barrier structure. A gate metal disposed on the barrier structure between the pair of S/D metals. The channel layer has a two-dimensional electron gas (2DEG) layer close to an interface between the channel layer and the barrier structure. A fluorine ion concentration in the channel layer adjacent to the 2DEG layer is greater than that away from the 2DEG layer.