A semiconductor device includes a first n type layer and a second n type layer that are sequentially disposed on a first surface of an n+ type silicon carbide substrate; a first trench and a second trench that are disposed at the second n type layer and are spaced apart from each other; a p type region surrounding a lateral surface and a lower surface of the first trench; an n+ type region disposed on the p type region and the second n type layer; a gate insulating layer disposed in the second trench; a gate electrode disposed on the gate insulating layer; an oxide layer disposed on the gate electrode; a source electrode disposed on the oxide layer and the n+ type region disposed in the first trench; and a drain electrode disposed at a second surface of the n+ type silicon carbide substrate.

A semiconductor device is provided in which a zener diode having a desired breakdown voltage and a capacitor in which voltage dependence of capacitance is reduced are mounted together, and various circuits are realized. The semiconductor device includes: a semiconductor layer; a first conductivity type well that is arranged in a first region of the semiconductor layer; a first conductivity type first impurity diffusion region that is arranged in the well; a first conductivity type second impurity diffusion region that is arranged in a second region of the semiconductor layer; an insulating film that is arranged on the second impurity diffusion region; an electrode that is arranged on the insulating film; and a second conductivity type third impurity diffusion region that is arranged at least on the first impurity diffusion region.

A nitride semiconductor device includes: a substrate; a buffer layer formed on the substrate; a laminated body formed by two or more cycles of semiconductor layers each including a first nitride semiconductor layer, and a second nitride semiconductor layer having a larger band gap than a band gap of the first nitride semiconductor layer, the first and second nitride semiconductor layers being laminated in this order on the buffer layer; a first electrode; and a second electrode. A channel layer is formed in each of the semiconductor layers at an interface between the first nitride semiconductor layer and the second nitride semiconductor layer. A carrier concentration of the channel layer in the uppermost semiconductor layer is lower than a carrier concentration of each of the channel layers of the other semiconductor layers.

There is formed a first concave portion that extends inside a semiconductor substrate from a main surface thereof. An insulating film is formed over the main surface, over a side wall and a bottom wall of the first concave portion so as to cover an element and to form a capped hollow in the first concave portion. A first hole portion is formed in the insulating film so as to reach the hollow in the first concave portion from an upper surface of the insulating film, and to reach the semiconductor substrate on the bottom wall of the first concave portion while leaving the insulating film over the side wall of the first concave portion. There is formed a second hole portion that reaches the conductive portion from the upper surface of the insulating film. The first and second hole portions are formed by the same etching treatment.

A semiconductor device includes a current spreading layer, a gate trench, a gate electrode, a first body region, a first source region, a second body region and a second source region. The first body region is beneath and in contact with the gate trench. The first source region is formed in the first body region. The second body region extends from a first surface of the current spreading layer into the current spreading layer and adjoins a first sidewall of the gate trench. The second source region is formed in the second body region and adjoins the first sidewall of the gate trench.

Vertical semiconductor devices with deep wells and associated fabrication methods are disclosed herein. A disclosed process for forming a semiconductor device includes forming, on a drift region having a first conductivity type, a deep well region for the semiconductor device. The deep well region can be formed by an implant. The deep well region has a second conductivity type. The deep well region of the second conductivity type leaves a portion of the surface of the drift region exposed. The process also includes epitaxially forming a semiconductor region that extends from the surface of the drift region to above the deep well region for the semiconductor device. The semiconductor region can be used as at least a part of the main operational current path of the semiconductor device when the semiconductor device is finished and is devoid of implant damage from the implant.

A semiconductor device according to one or more embodiments is disclosed that may include a p-type first semiconductor region, an n-type second semiconductor region formed on a surface of the first semiconductor region, an n-type third semiconductor region formed by separating from the second semiconductor region, an n-type fourth semiconductor region having a higher impurity concentration than the second semiconductor region, an insulating film arranged on the semiconductor substrate, a gate electrode arranged via the insulating film between the second semiconductor region and the third semiconductor region, a first main electrode electrically connected to the second semiconductor region, a second main electrode electrically connected to the fourth semiconductor region, a p-type fifth semiconductor region on the third semiconductor region, which has a higher impurity concentration than that of the first semiconductor region, and an auxiliary electrode connected to the fifth semiconductor region.

A semiconductor device includes substrate, a first gate structure, a second gate structure, and an epitaxy layer. The first gate structure and the second gate structure are over the substrate, in which the first gate structure and the second gate structure each comprises a shielding electrode, a gate electrode over the shielding electrode, and a first gate dielectric layer vertically separating the shielding electrode from the gate electrode. The epitaxy layer is over the substrate and cups an underside of the first gate structure and the second gate structure, in which the epitaxy layer comprises a doped region laterally between the first gate dielectric layer of the first gate structure and the first gate dielectric layer of the second gate structure, a dopant concentration of the doped region being non-uniform along a lateral direction.

A super junction MOSFET device, including: a substrate having a first conductive type; a buffer layer having the first conductive type and disposed on the substrate; a super junction structure disposed on the buffer layer and including multiple first conductive type pillars and multiple second conductive type pillars alternately arranged in a transverse direction, several second conductive type pillars being partially and/or wholly displaced to provide two or more different transverse dimensions for the first conductive type pillars; a body region having the second conductive type and disposed on a top of the second conductive type pillar; a source structure located within the body region and including a source region having the first conductive type and an ohmic contact region having the second conductive type which contacts with the source region; and a gate structure in contact with the first conductive type pillar and the source structure.

A compound semiconductor substrate has a Si (silicon) substrate, a first Al nitride semiconductor layer which is a graded layer formed on the Si substrate and whose Al concentration decreases as the distance from the Si substrate increases along the thickness direction, a GaN (gallium nitride) layer formed on the first Al nitride semiconductor layer and having a lower average Al concentration than the average Al concentration of the first Al nitride semiconductor layer, and a second Al nitride semiconductor layer formed on the GaN layer and having a higher average Al concentration than the average Al concentration of the GaN layer. The threading dislocation density at any position in the thickness direction within the second Al nitride semiconductor layer is lower than the threading dislocation density at any position in the thickness direction within the first Al nitride semiconductor layer.