An IC includes logic cells, selected from a standard cell library, and fill cells, configured for compatibility with the standard logic cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (NCEM). The IC includes such NCEM-enabled fill cells configured to enable detection and/or measurement of a variety of short-circuit failure modes, including at least one chamfer-short-related failure mode, one AACNT-short-related failure mode, one GATE-short-related failure mode, and one GATECNT-short-related failure mode.

An IC includes first and second designs of experiments (DOEs), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (NCEM). The first DOE contains fill cells configured to enable non-contact (NC) detection of merged-via opens, and the second DOE contains fill cells configured to enable NC detection of snake opens.

Techniques for device isolation for III-V semiconductor substrates are provided. In one aspect, a method of fabricating a III-V semiconductor device is provided. The method includes the steps of: providing a substrate having an indium phosphide (InP)-ready layer; forming an iron (Fe)-doped InP layer on the InP-ready layer; forming an epitaxial III-V semiconductor material layer on the Fe-doped InP layer; and patterning the epitaxial III-V semiconductor material layer to form one or more active areas of the device. A III-V semiconductor device is also provided.

A transistor with favorable electrical characteristics, a transistor with stable electrical characteristics, or a highly integrated semiconductor device is provided. In a top-gate transistor in which an oxide semiconductor is used for a semiconductor layer where a channel is formed, elements are introduced to the semiconductor layer in a self-aligned manner after a gate electrode is formed. After that, a side surface of the gate electrode is covered with a structure body. The structure body preferably contains silicon oxide. A first insulating layer is formed to cover the semiconductor layer, the gate electrode, and the structure body. A second insulating layer is formed by a sputtering method over the first insulating layer. Oxygen is introduced to the first insulating layer when the second insulating layer is formed.

A high-voltage semiconductor structure including a substrate, a first doped region, a well, a second doped region, a third doped region, a fourth doped region, and a gate structure is provided. The substrate has a first conductive type. The first doped region has the first conductive type and is formed in the substrate. The well has a second conductive type and is formed in the substrate. The second doped region has the second conductive type and is formed in the first doped region. The third doped region has the first conductive type and is formed in the well. The fourth doped region has the second conductive type and is formed in the well. The gate structure is disposed over the substrate and partially covers the first doped region and the well.

A semiconductor device includes: an n type semiconductor layer including an active region and an inactive region; an element structure formed in the active region and including at least an active side p type layer to form pn junction with n type portion of the n type semiconductor layer; an inactive side p type layer formed in the inactive region and forming pn junction with the n type portion of the n type semiconductor layer; a first electrode electrically connected to the active side p type layer in a front surface of the n type semiconductor layer; a second electrode electrically connected to the n type portion of the n type semiconductor layer in a rear surface of the n type semiconductor layer; and a crystal defect region formed in both the active region and the inactive region and having different depths in the active region and the inactive region.

An IC includes first and second designs of experiments (DOES), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (NCEM). The first DOE contains fill cells configured to enable non-contact (NC) detection of merged-via opens, and the second DOE contains fill cells configured to enable NC detection of metal island opens.

An IC includes first and second designs of experiments (DOES), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (NCEM). The first DOE contains fill cells configured to enable non-contact (NC) detection of side-to-side shorts, and the second DOE contains fill cells configured to enable NC detection of chamfer shorts.

A semiconductor device includes a first electrode, a second electrode, a first semiconductor region of a first conductivity type that is between the first electrode and the second electrode. A second semiconductor region is adjacent to the first semiconductor region along a first direction and includes a second conductivity type material. A first insulating region is provided within the second semiconductor region. A third electrode is provided on the first semiconductor region via a second insulating region.

An IC includes logic cells, selected from a standard cell library, and fill cells, configured for compatibility with the standard logic cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (NCEM). The IC includes such NCEM-enabled fill cells configured to enable detection and/or measurement of a variety of open-circuit and short-circuit failure modes, including at least one via-open-related failure mode, one AACNT-short-related failure mode, one GATECNT-short-related failure mode, and one TS-short-related failure mode.