Disclosed is a method. The method includes forming a metal layer on a first surface of a semiconductor body; irradiating the metal layer with particles to move metal atoms from the metal layer into the semiconductor body and form a metal atom containing region in the semiconductor body; and annealing the semiconductor body. The annealing includes heating at least the metal atom containing region to a temperature of less than 500 C.

A semiconductor structure includes a semiconductor substrate, and an NMOS device at a surface of the semiconductor substrate, wherein the NMOS device comprises a Schottky source/drain extension region. The semiconductor structure further includes a PMOS device at the surface of the semiconductor substrate, wherein the PMOS device comprises a source/drain extension region comprising only non-metal materials. Schottky source/drain extension regions may be formed for both PMOS and NMOS devices, wherein the Schottky barrier height of the PMOS device is reduced by forming the PMOS device over a semiconductor layer having a low valence band.

A semiconductor device according to the embodiments includes a SiC layer having a first plane, an insulating layer, and a region between the first plane and the insulating layer, the region including at least one element in the group consisting of Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), and Ba (barium), a full width at half maximum of a concentration peak of the element being equal to or less than 1 nm, and when a first area density being an area density of Si (silicon) and C (carbon) including a bond which does not bond with any of Si and C in the SiC layer at the first plane and a second area density being an area density of the element, the second area density being equal to or less than of the first area density.

A method for manufacturing a semiconductor device, includes: a preparation step, a flow step, and a processing step. The preparation step prepares an etching solution by dissolving titanium in an ammonia-hydrogen peroxide solution in advance before use of the ammonia-hydrogen peroxide solution for etching. The flow step flows the etching solution after the preparation step so that a concentration of the etching solution in a processing bath is constant. The processing step etches a metal film on a semiconductor wafer with the etching solution by putting in the processing bath the semiconductor wafer having a resist film and the metal film after the flow step is started. The metal film is preferably formed of titanium, and a temperature of the etching solution is preferably adjusted by flowing the etching solution so that the etching solution flows via a temperature controller.

A method for producing a semiconductor device includes: depositing a barrier layer on a first surface of a semiconductor body having active regions of a semiconductor device; forming a contact layer that at least partially covers the barrier layer, the barrier layer being configured to prevent a material of the contact layer from diffusing into the semiconductor body; forming a first passivation layer on the contact layer and on exposed surfaces of the barrier layer; in a first etching process, removing the first passivation layer from above the barrier layer so as to uncover sections of the barrier layer; and in a second etching process, removing at least some sections of the barrier layer uncovered by the first etching process

Provided is a semiconductor package including a Si substrate, a drift layer, a buffer layer, an anode electrode, a trench, a semiconductor apparatus, an anode terminal, a cathode terminal, and a sealing resin.

A tuning method for active metamaterials using IGZO Schottky diodes, wherein the IGZO Schottky diode comprises a substrate, a Schottky electrode, amorphous IGZO active layer, and an ohmic electrode from the bottom up. The method comprises steps as follows: (1) Metamaterials are used as the Schottky electrodes, and amorphous IGZO active layers are used to fully cover the capacitive gap structures in the metamaterials; such capacitive structures in the metamaterials are bonded to the amorphous IGZO active layers to form Shottky barriers; (2) The resulting IGZO Schottky diodes from step (1) are used to tune the metamaterials dynamically.

A tuning method for active metamaterials using IGZO Schottky diodes, wherein the IGZO Schottky diode comprises a substrate, a Schottky electrode, amorphous IGZO active layer, and an ohmic electrode from the bottom up. The method comprises steps as follows: (1) Metamaterials are used as the Schottky electrodes, and amorphous IGZO active layers are used to fully cover the capacitive gap structures in the metamaterials; such capacitive structures in the metamaterials are bonded to the amorphous IGZO active layers to form Shottky barriers; (2) The resulting IGZO Schottky diodes from step (1) are used to tune the metamaterials dynamically.

Apparatus and circuits with dual threshold voltage transistors and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a first layer comprising a first III-V semiconductor material formed over the substrate; a first transistor formed over the first layer, and a second transistor formed over the first layer. The first transistor comprises a first gate structure comprising a first material, a first source region and a first drain region. The second transistor comprises a second gate structure comprising a second material, a second source region and a second drain region. The first material is different from the second material.

A method for manufacturing nitride semiconductor device includes a second step of forming, on a gate layer material film, a gate electrode film that is a material film of a gate electrode, a third step of selectively etching the gate electrode film to form the gate electrode 22 of a ridge shape, and a fourth step of selectively etching the gate layer material film to form a semiconductor gate layer 21 of a ridge shape with the gate electrode 22 disposed at a width intermediate portion of a front surface thereof. The third step includes a first etching step for forming a first portion 22A from an upper end to a thickness direction intermediate portion of the gate electrode 22 and a second etching step being a step differing in etching condition from the first etching step and being for forming a remaining second portion 22B of the gate electrode.