A trench capacitor manufacturing method is provided. The method includes forming a deep trench in a wafer, forming a trench capacitor structure including a plurality of dielectric films and a plurality of conductive layers in the deep trench; determining if the wafer has a tensile stress based on the forming of the trench capacitor structure; performing a high temperature heat treatment to the trench capacitor structure to change a form of the wafer to a direction that offsets the tensile stress; forming an inter-layer insulating film on the trench capacitor structure; and forming a metal interconnect on the inter-layer insulating film.

Method for producing a trench capacitor structure, including the steps of providing a silicon substrate with a trench structure comprising a plurality of recesses in a main surface of the silicon substrate; forming a first silicon dioxide layer at least in the recesses of the silicon substrate; depositing a first silicon nitride layer on the first silicon dioxide layer; depositing a second silicon dioxide layer on the first silicon nitride layer by depositing a polycrystalline silicon layer and oxidizing the polycrystalline silicon layer; and depositing a second silicon nitride layer on the second silicon dioxide layer.

A semiconductor device includes a substrate and a deep trench capacitor structure. The deep trench capacitor structure includes a plurality of electrode layers and a plurality of dielectric layers alternately stacked, a contact via and at least one pair of spacers. The electrode layers and the dielectric layers form a mirror staircase portion over the substrate and a deep trench portion in the substrate. The contact via is electrically connected to a bottommost one of the electrode layers in the mirror staircase portion. The at least one pair of spacers is disposed on the mirror staircase portion and surrounds the contact via.

A microelectronic device includes an integrated deep trench in a substrate, with a field oxide layer on the substrate. The integrated deep trench includes a of deep trench extending into semiconductor material of the substrate, a deep trench sidewall dielectric layer contacting the substrate and an electrically conductive trench-fill material contacting the deep trench sidewall dielectric layer. The conductive trench-fill material is covered during the formation of the field oxide layer to minimize the trench-fill seam void volume. Minimizing the trench-fill seam void volume minimizes optical defectivity observed in subsequent yield enhancement. The integrated deep trench may be configured as a capacitor or may be configured as a contact to the underlying substrate.

The present application relates to a silicon-on-insulator transverse device and a manufacturing method therefor. The device comprises: a substrate; a buried dielectric layer provided on the substrate; a drift region provided on the buried dielectric layer, a vertical conductive structure extending downwards from the drift region to the buried dielectric layer; a low-K dielectric provided in the buried dielectric layer and surrounding the bottom of the vertical conductive structure; and a dielectric layer provided on a side surface of the vertical conductive structure and located between the vertical conductive structure and the drift region and above the low-K dielectric.

A semiconductor die includes an array of first capacitor regions, each of the first capacitor regions including multiple first capacitor cell structures, wherein each first capacitor cell structure includes a plurality of first trench segments characterized by a first trench length, a first trench width, and a first trench spacing, and a first air gap width in a gap-filling material. The semiconductor die also includes a plurality of second capacitor regions interspersed in the array of first capacitor regions, each of the second capacitor region including multiple second capacitor cell structures, wherein each second capacitor cell structures includes a plurality of second trench segments characterized by a second trench length, a second trench width, a second trench spacing, and a second air gap width in the gap-filling material.

An electronic component comprising a 3D capacitive structure includes a substrate having a contoured surface comprising a plurality of wells extending from the surface into the substrate body, a dielectric formed over, and conforming to the shape of, the contoured surface, and a first electrode formed over the dielectric and conforming to the contoured surface shape. The substrate constitutes a second electrode and the dielectric is interposed between it and the first electrode. Portions of the dielectric are exposed through openings at the base of the contoured surface and contact an insulating layer formed under the substrate, reducing the electrostatic field arising in the contacted portions of the dielectric when a potential difference is applied between the first and second electrodes. The openings at the bottom of the wells are obturated by the dielectric, defining blind holes within the wells, and the first electrode is in the blind holes.

A first source drain region directly adjacent to a first nanosheet stack, a second source drain region directly adjacent to a second nanosheet stack, an inner electrode of a capacitor between the first source drain region and the second source drain region and a non-conducting layer sandwiched between the inner electrode and the first source drain region. A first source drain region directly adjacent to a first nanosheet stack, a second source drain region directly adjacent to a second nanosheet stack, an inner electrode of a capacitor between the first source drain region and the second source drain region, a first liner sandwiched between the inner electrode and the first source drain region, and a second liner sandwiched between the inner electrode and the second source drain region.

A semiconductor structure includes a substrate, a capacitor structure, and a first metal via. The capacitor structure is over the substrate, in which the capacitor structure includes a group of capacitor units extending into the substrate, the capacitor units are arranged along a first direction, and the capacitor units have a lengthwise direction along a second direction perpendicular to the first direction. The capacitor structure includes a first metallic electrode layer, a node dielectric layer over the first metallic electrode layer, and a second metallic electrode layer over the node dielectric layer. The first metal via is over the capacitor structure and in contact with the second metallic electrode layer of the capacitor structure, in which a length of the first metal via is greater than a width of the first metal via from a top view.

Embodiments relate to a semiconductor structure and a formation method thereof. The method for forming a semiconductor structure includes: forming a substrate and a semiconductor layer positioned above the substrate, where the semiconductor layer includes first trenches spaced along a first direction, the first direction being a direction parallel to a top surface of the substrate; forming, in the semiconductor layer, an isolation trench positioned below the first trenches, where the isolation trench extends along the first direction and continuously communicates with the first trenches; forming a first spacer at least positioned in the isolation trench; and forming a capacitor above the first spacer. The semiconductor structure and the formation method thereof reduce electric leakage between the substrate and the capacitor, thereby improving electrical performance of the semiconductor structure.