An image sensor employing deep trench spacing isolation is provided. A plurality of pixel sensors is arranged over or within a semiconductor substrate. A trench is arranged in the semiconductor substrate around and between adjacent ones of the plurality of pixel sensors, and the trench has a gap located between sidewalls of the trench. A cap is arranged over or within the trench at a position overlying the gap. The cap seals the gap within the trench. A method of manufacturing the image sensor is also provided.

An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.

A semiconductor chip includes a substrate including a surface, an active transistor region and a substrate contact region formed on the substrate, a shallow trench isolation (STI) area formed in the surface and disposed at least partially between the active transistor region and the substrate contact region, and at least one capacitor at least partially buried in the STI area.

An integrated circuit including an integrated trench capacitor in a substrate. The trench capacitor includes a plurality of deep trenches extending into the substrate, the trenches filled with a conductive trench-fill material. A first subset of the trenches located in an N-type well and a second subset of the trenches located in a P-type well. A first capacitor terminal connects the conductive trench-fill material in the first subset of trenches and the conductive trench-fill material in the second subset of trenches. A second capacitor terminal connects the N-type well and the P-type well.

A semiconductor structure and method for fabricating it are disclosed. The method includes: providing a semiconductor substrate including a BOX layer, at least one fin structure, a DTC, an isolation layer and an HARP layer, the semiconductor substrate divided into a fin structure region and a DT region; thinning the HARP layer, with the remaining portion of the HARP layer being retained above the BOX layer; removing the isolation layer and the HARP layer from the fin structure region; forming a first oxide layer over the semiconductor substrate; and forming layer-stacked structures and sidewall spacers. According to the present invention, the thinned HARP layer being retained above the BOX layer and is subsequently removed only from the fin structure region.

A semiconductor die includes an array of first capacitor regions, each of the first capacitor regions including multiple first capacitor cell structures, wherein each first capacitor cell structure includes a plurality of first trench segments characterized by a first trench length, a first trench width, and a first trench spacing, and a first air gap width in a gap-filling material. The semiconductor die also includes a plurality of second capacitor regions interspersed in the array of first capacitor regions, each of the second capacitor region including multiple second capacitor cell structures, wherein each second capacitor cell structures includes a plurality of second trench segments characterized by a second trench length, a second trench width, a second trench spacing, and a second air gap width in the gap-filling material.

An electronic device including a substrate with a trench and an inductor disposed on the substrate is provided. The inductor includes a first conductive layer and a second conductive layer. The first conductive layer is conformally disposed on the substrate. At least a portion of the first conductive layer is disposed in the trench. The first conductive layer has a first end portion and a second end portion. The second conductive layer is conformally disposed on the first conductive layer. The second conductive layer has a first end portion and a second end portion on the first end portion of the first conductive layer and the second end portion of the first conductive layer, respectively. The first end portion of the second conductive layer is electrically connected with the second end portion of the first conductive layer.

A capacitor structure that includes a silicon substrate having a trench structure formed therein; a dielectric disposed over a surface of the trench structure, conformal to the surface of the trench structure; and a filling layer disposed over the dielectric layer and into the trench structure, the filling layer including a conductive layer and a polymer layer.

A method for forming a poly-insulator-poly (PIP) capacitor is disclosed. A semiconductor substrate having a capacitor forming region is provided. A first capacitor dielectric layer is formed on the capacitor forming region. A first poly electrode is formed on the first capacitor dielectric layer. A second capacitor dielectric layer is formed on the first poly electrode. A second poly electrode is formed on the second capacitor dielectric layer. A third poly electrode is formed adjacent to a first sidewall of the second poly electrode. A third capacitor dielectric layer is formed between the third poly electrode and the second poly electrode. A fourth poly electrode is formed adjacent to a second sidewall of the second poly electrode that is opposite to the first sidewall. A fourth capacitor dielectric layer is formed between the fourth poly electrode and the second poly electrode.

A semiconductor package is provided and includes: a lower redistribution layer; a capacitor chip on the lower redistribution layer; an interposer chip on the lower redistribution layer, horizontally spaced apart from the capacitor chip, and connected to the lower redistribution layer; a mold layer surrounding the capacitor chip and the interposer chip; and an upper redistribution layer on a top surface of the mold layer and connected to the capacitor chip and the interposer chip. The capacitor chip includes a capacitor substrate and a capacitor device in the capacitor substrate, and the capacitor device includes: a top electrode pad; top electrodes on a bottom surface of the top electrode pad, a capacitor dielectric layer on the top electrodes with a uniform thickness; and a bottom electrode on the capacitor dielectric layer such as to commonly cover the top electrodes.