An integrated power module having a depletion mode device and an enhancement mode device that is configured to prevent an accidental on-state condition for the depletion mode device during a gate signal loss is disclosed. In particular, the disclosed integrated power module is structured to provide improved isolation and thermal conductivity. The structure includes a substrate having a bottom drain pad for the depletion mode device disposed on the substrate and an enhancement mode device footprint-sized cavity that extends through the substrate to the bottom drain pad. A thermally conductive and electrically insulating slug substantially fills the cavity to provide a higher efficient thermal path between the enhancement mode device and the bottom drain pad for the depletion mode device.

Apparatus and circuits with dual threshold voltage transistors and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a first layer comprising a first III-V semiconductor material formed over the substrate; a first transistor formed over the first layer, and a second transistor formed over the first layer. The first transistor comprises a first gate structure comprising a first material, a first source region and a first drain region. The second transistor comprises a second gate structure comprising a second material, a second source region and a second drain region. The first material is different from the second material.

Apparatus and circuits with dual threshold voltage transistors and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a first layer comprising a first III-V semiconductor material formed over the substrate; a first transistor formed over the first layer, and a second transistor formed over the first layer. The first transistor comprises a first gate structure comprising a first material, a first source region and a first drain region. The second transistor comprises a second gate structure comprising a second material, a second source region and a second drain region. The first material is different from the second material.

A semiconductor device has a substrate, and a heterojunction structure formed by two group III-V compound layers above the substrate. A first gate electrode is deposited above a first group III-V compound layer and a second group III-V compound layer, the first gate electrode is electrically connected to a first gate terminal. A second gate electrode is deposited above the first group III-V compound layer and the second group III-V compound layer, the second gate electrode is electrically connected to a second gate terminal. A source electrode is deposited above the heterojunction structure, the source electrode is electrically connected to a source terminal. A first drain electrode deposited above the heterojunction structure, the first drain electrode is electrically connected to a drain terminal. A second drain electrode deposited above the heterojunction structure, the second drain electrode is electrically connected to the first gate terminal.

A bidirectional switch for use in high power electronics, being compact and having low on-resistance. The bidirectional switch includes several layers epitaxially grown on a substrate, the epitaxial layer comprising a channel layer and a barrier layer grown on the channel layer, an interface of the barrier layer and the channel layer defining a heterojunction that induces a two-dimensional electron gas (2DEG) within the channel layer, the 2DEG extending laterally at the interface between the barrier and channel layers. The bidirectional switch includes two source contacts, which are ohmic, each in contact with the 2DEG channel layer, but near opposite ends of the 2DEG. The bidirectional switch further includes two gate electrodes disposed over the barrier layer and between the two source contacts. Voltages applied to these gate electrodes controls the current flow in the bidirectional switch between the two contacts.

A GaN HEMT with a stacked multilayer 3D structure is proposed, which is formed by re-growing a GaN layer, fabricated a second HEMT on a dielectric protective layer and connected the source, gate or drain electrodes of the respective GaN HEMT. Process is repeated to form at least three layers GaN HEMT structure, one stacked on top of the other, with each electrode of individual GaN HEMT connected by a deep etching process. Bonding pads of the HEMT device are formed on the uppermost layer of the device. The multilayer 3D GaN HEMT device will be manufactured based on stacking one layer of GaN HEMT following one layer of protection layer. In this way, the layout area of the GaN HEMT device can be reduced and the current density per unit area can be increased, thereby reducing the overall packaged volume.

A GaN HEMT with a stacked multilayer 3D structure is proposed, which is formed by re-growing a GaN layer, fabricated a second HEMT on a dielectric protective layer and connected the source, gate or drain electrodes of the respective GaN HEMT. Process is repeated to form at least three layers GaN HEMT structure, one stacked on top of the other, with each electrode of individual GaN HEMT connected by a deep etching process. Bonding pads of the HEMT device are formed on the uppermost layer of the device. The multilayer 3D GaN HEMT device will be manufactured based on stacking one layer of GaN HEMT following one layer of protection layer. In this way, the layout area of the GaN HEMT device can be reduced and the current density per unit area can be increased, thereby reducing the overall packaged volume.

A semiconductor device, according to an embodiment, includes a main transistor, a sub transistor that is connected to one terminal of the main transistor, and a resistive element that is connected between another terminal of the main transistor and the sub transistor. The main transistor includes a main channel layer and a barrier layer, which is positioned on the main channel layer and contains a material having an energy band gap different from that of the main channel layer. The sub transistor includes a first sub drift region having a first 2-dimensional electron gas (2DEG) region. The resistive element includes a channel pattern that is electrically connected between a sensing electrode of the sub transistor and a main source electrode of the main transistor, and the channel pattern includes a second sub drift region having a second 2DEG region.

A semiconductor device, according to an embodiment, includes a main transistor, a sub transistor that is connected to one terminal of the main transistor, and a resistive element that is connected between another terminal of the main transistor and the sub transistor. The main transistor includes a main channel layer and a barrier layer, which is positioned on the main channel layer and contains a material having an energy band gap different from that of the main channel layer. The sub transistor includes a first sub drift region having a first 2-dimensional electron gas (2DEG) region. The resistive element includes a channel pattern that is electrically connected between a sensing electrode of the sub transistor and a main source electrode of the main transistor, and the channel pattern includes a second sub drift region having a second 2DEG region.

A semiconductor device includes third active regions that connect two finger-end portions of field effect transistors (FETs) spaced apart from each other, and includes, above the third active regions, portions of a third nitride semiconductor layer that includes P-type impurities.