The techniques described herein relate to a transistor, including a substrate including SiC-4H, MgO, or AlGaO.sub.3; an epitaxial channel layer on the substrate, and a gate layer on the epitaxial channel layer. The epitaxial channel layer can include Ga.sub.2O.sub.3 with a first bandgap, wherein the Ga.sub.2O.sub.3 is: -Ga.sub.2O.sub.3 with a hexagonal or trigonal crystal symmetry; -Ga.sub.2O.sub.3 with an orthorhombic crystal symmetry; or -Ga.sub.2O.sub.3 with a cubic crystal symmetry. The gate layer can include an oxide material with a second bandgap, where the second bandgap is wider than the first bandgap. The transistor can also include electrical contacts including: a source electrical contact coupled to the epitaxial channel layer; a drain electrical contact coupled to the epitaxial channel layer; and a gate electrical contact coupled to the gate layer.

The present disclosure relates to a semiconductor structure including a superlattice with repeating unit cells of a narrow bandgap (NBG) layer and a wide bandgap (WBG) layer. The NBG and WBG layers include an NBG and a WBG polar semiconductor material, respectively. An energy barrier region is in contact with the superlattice, including a total of N layers of alternating the WBG and NBG polar semiconductor materials, wherein a total thickness of the energy barrier region is equal to a thickness of N/2 unit cells of the superlattice, and wherein N is an even number greater than or equal to 4. Layers of the N layers of the energy barrier region, either WBG layers or NBG layers, are both thicker and thinner than a corresponding layer (either WBG or NBG) of the unit cell of the superlattice to form the energy barrier.