The invention disclosed a preparation method for a high-voltage LED device integrated with a pattern array, comprising the following process steps: providing a substrate, and forming a N-type GaN limiting layer, an epitaxial light-emitting layer and a P-type GaN limiting layer on the substrate in sequence; isolating the N-GaN limiting layer, the epitaxial light-emitting layer and the P-GaN limiting layer on the substrate into at least two or more independent pattern units by means of photo lithography and etching process, wherein each of the pattern unit is in a triangular shape, and very two adjacent pattern units are arranged in an opposing and crossed manner to form a quadrangle, and the quadrangles formed by a plurality of adjacent pattern units are distributed in array; and connecting each pattern unit with metal wires to form a series connection and/or a parallel connection, thereby forming a plurality of interconnected LED chips. For the purpose of improving the current distribution so as to increase the luminescent efficiency of the device, a current blocking layer is also arranged beneath the P-type metal contact of each unit; in addition, an insulation material is also arranged to cover the surface of the chip so as to achieve the purposes of protecting the chip and increasing the light extraction efficiency of the chip.

Diode includes first metal layer, coupled to p-type III-N layer and to first terminal, has a substantially equal lateral size to the p-type III-N layer. Central portion of light emitting region on first side and first metal layer includes first via that is etched through p-type portion, light emitting region and first part of n-type III-N portion. Second side of central portion of light emitting region that is opposite to first side includes second via connected to first via. Second via is etched through second part of n-type portion. First via includes second metal layer coupled to intersection between first and second vias. Electrically-insulating layer is coupled to first metal layer, first via, and second metal layer. First terminals are exposed from electrically-insulating layer. Third metal layer including second terminal is coupled to n-type portion on second side of light emitting region and to second metal layer through second via.

A contact to a semiconductor heterostructure is described. In one embodiment, there is an n-type semiconductor contact layer. A light generating structure formed over the n-type semiconductor contact layer has a set of quantum wells and barriers configured to emit or absorb target radiation. An ultraviolet transparent semiconductor layer having a non-uniform thickness is formed over the light generating structure. A p-type contact semiconductor layer having a non-uniform thickness is formed over the ultraviolet transparent semiconductor layer.

A light-emitting device includes: a rectangular shape with a 1.sup.st side, a 2.sup.nd side opposite to the 1.sup.st side, and a 3.sup.rd side connecting the 1.sup.st and the 2.sup.nd sides; a first electrode pad formed adjacent to the 3.sup.rd side; a second electrode pad formed adjacent to the 2.sup.nd side; a first extension electrode, extending from the first electrode pad in a direction away from the 3.sup.rd side and bended toward the 2.sup.nd side; and a second extension electrode, including a first and a second branches respectively extending from the second electrode pad; wherein a distance between the first electrode pad and the 3.sup.rd side is smaller than a distance between the second electrode pad and the 3.sup.rd side; wherein an end portion of the first branch includes a first arc bending to the 3.sup.rd side and a minimum distance between the first branch and the 1.sup.st side is smaller than a minimum distance between the second branch and the 1.sup.st side.

Disclosed are a light emitting device, a method of manufacturing a light emitting device, a light emitting device package and a lighting system. The light emitting device includes a substrate; a first conductive semiconductor layer on the substrate; an active layer on the first conductive semiconductor layer; a second conductive semiconductor layer on the active layer; a contact layer on the second conductive semiconductor layer; an insulating layer on the contact layer; a first branch electrode electrically connected to the first conductive semiconductor layer; a plurality of first via electrodes connected to the first branch electrode and electrically connected to the first conductive semiconductor layer by passing through the insulating layer; a first pad electrode electrically connected to the first branch electrode; a second pad electrode contacts the contact layer by passing through the insulating layer; a second branch electrode connected to the second pad electrode and disposed on the insulating layer; and a plurality of second via electrodes provided through provided through the insulating layer to electrically connect the second branch electrode to the contact layer.

The invention disclosed a preparation method for a high-voltage LED device integrated with a pattern array, comprising the following process steps: providing a substrate, and forming a N-type GaN limiting layer, an epitaxial light-emitting layer and a P-type GaN limiting layer on the substrate in sequence; isolating the N-GaN limiting layer, the epitaxial light-emitting layer and the P-GaN limiting layer on the substrate into at least two or more independent pattern units by means of photo lithography and etching process, wherein each of the pattern unit is in a triangular shape, and very two adjacent pattern units are arranged in an opposing and crossed manner to form a quadrangle, and the quadrangles formed by a plurality of adjacent pattern units are distributed in array; and connecting each pattern unit with metal wires to form a series connection and/or a parallel connection, thereby forming a plurality of interconnected LED chips. For the purpose of improving the current distribution so as to increase the luminescent efficiency of the device, a current blocking layer is also arranged beneath the P-type metal contact of each unit in addition, an insulation material is also arranged to cover the surface of the chip so as to achieve the purposes of protecting the chip and increasing the light extraction efficiency of the chip.

A backlight unit includes a backlight module with a printed circuit board including blocks and MJT LEDs disposed on the blocks, respectively and a backlight control module generating a signal for drive control of each of the blocks, wherein each of the blocks comprises at least one MJT LED, and the backlight control module includes a drive controller for On/Off control and dimming control of each of the blocks.

A light emitting diode chip includes an epitaxial layer with a plurality of recess portions and protrusion portions over the top layer; a light transmission layer, located between top ends of adjacent protrusion portions and forming holes with the recess portions. The light transmission layer has a horizontal dimension larger than a width of the top ends of two adjacent protrusion portions, and serves as current blocking layer; a current spreading layer covering the surface of the light transmission layer and the surface of an epitaxial layer of a non-mask light transmission layer. As the refractive index of the light transmission layer is between those of the epitaxial layer and the hole, indicating a difference of refractive index between the light transmission layer and the epitaxial layer, the probability of scattering generated when light from a luminescent layer emits upwards can be increased, thus avoiding light absorption by electrodes and improving light extraction efficiency.

This invention discloses a method for the fabrication of GaN-based vertical cavity surface-emitting devices featuring a silicon-diffusion defined current blocking layer (CBL). Such devices include vertical-cavity surface-emitting laser (VCSEL) and resonant-cavity light-emitting diode (RCLED). The silicon-diffused P-type GaN region can be converted into N-type GaN and thereby attaining a current blocking effect under reverse bias. And the surface of the silicon-diffused area is flat so the thickness of subsequent optical coating is uniform across the emitting aperture. Thus, this method effectively reduces the optical-mode field diameter of the device, significantly decreases the spectral width of LED, and produces single-mode emission of VCSEL.

A light emitting element includes: a semiconductor structure including: a substrate, an n-side nitride semiconductor layer located on the substrate, and a p-side nitride semiconductor layer located on the n-side nitride semiconductor layer, wherein a p-side nitride semiconductor side of the semiconductor structure is a light extraction face side, and an n-side nitride semiconductor side of the semiconductor structure is a mounting face side; a first protective layer located on and in direct contact with an upper face of the p-side nitride semiconductor layer in a region corresponding to the peripheral portion of the p-side nitride semiconductor layer; and a current diffusion layer located on and in direct contact with an upper face of the p-side nitride semiconductor layer in a region corresponding to the area inside of the peripheral portion. The current diffusion layer does not overlap the first protective layer in a top view.