An apparatus includes a p-type semiconductor material, an n-type semiconductor material, and an active region disposed between the p-type semiconductor material and the n-type semiconductor material. The active region emits light in response to a voltage applied across the active region, and the active region includes a quantum well region, a barrier region, and a capping region. The barrier region is disposed to confine charge carriers in the quantum well region. The capping region is disposed between the quantum well region and the barrier region, and the capping region is adjacent to the quantum well region to stabilize a material composition of the quantum well region. The quantum well region, the barrier region, and the capping region collectively form a first tri-layer structure.

An optoelectronic semiconductor chip includes a semiconductor layer sequence having at least one active layer. Furthermore, the semiconductor chip has a top-side contact structure on a radiation main side of the semiconductor layer sequence and an underside contact structure on an underside situated opposite to the radiation main side. Furthermore, the semiconductor chip includes at last two trenches that extend from the radiation main side towards the underside. As seen in a plan view of the radiation main side, the top-side contact structure and the underside contact structure are arranged in a manner spaced apart from one another. Likewise as seen in a plan view of the radiation main side, the trenches are located between the top-side contact structure and the underside contact structure.

The invention disclosed a preparation method for a high-voltage LED device integrated with a pattern array, comprising the following process steps: providing a substrate, and forming a N-type GaN limiting layer, an epitaxial light-emitting layer and a P-type GaN limiting layer on the substrate in sequence; isolating the NGaN limiting layer, the epitaxial light-emitting layer and the PGaN limiting layer on the substrate into at least two or more independent pattern units by means of photo lithography and etching process, wherein each of the pattern unit is in a triangular shape, and very two adjacent pattern units are arranged in an opposing and crossed manner to form a quadrangle, and the quadrangles formed by a plurality of adjacent pattern units are distributed in array; and connecting each pattern unit with metal wires to form a series connection and/or a parallel connection, thereby forming a plurality of interconnected LED chips. For the purpose of improving the current distribution so as to increase the luminescent efficiency of the device, a current blocking layer is also arranged beneath the P-type metal contact of each unit in addition, an insulation material is also arranged to cover the surface of the chip so as to achieve the purposes of protecting the chip and increasing the light extraction efficiency of the chip.

There is provided a Group III nitride semiconductor light-emitting device in which electrons and holes are suppressed to be captured by threading dislocation, and a production method therefor. The light-emitting device comprises an n-type semiconductor layer, a light-emitting layer on the n-type semiconductor layer, a p-type semiconductor layer on the light-emitting layer. The light-emitting device has a plurality of pits extending from the n-type semiconductor layer to the p-type semiconductor layer. The n-type semiconductor layer includes an n-side electrostatic breakdown preventing layer. The n-side electrostatic breakdown preventing layer comprises an n-type GaN layer containing starting point of the pits, and an ud-GaN layer disposed adjacent to the n-type GaN layer and containing a part of the pits. At least one of the n-type GaN layer and the ud-GaN layer has an In-doped layer. The In composition ratio of the In-doped layer is more than 0 and not more than 0.0035.

The invention provides ultraviolet (UV) light-emitting diodes (LEDs). The UV LEDs can comprise abase layer including p-type SiC or p-type AlGaN, an active layer, and an n-AlGaN layer, wherein the active layer is disposed between the base layer and the n-AlGaN layer. In some embodiments, the absorption losses in p-SiC can be decreased or prevented by incorporating a conductive AlGaN Distributed Bragg Reflector (DBR) between the p-type SiC layer and the active layer. In some embodiments, the n-AlGaN layer can be textured to increase the extraction efficiency (EE). In some embodiments, the external quantum efficiency of the LEDs can be 20-30% or more.

Diode includes first metal layer, coupled to p-type III-N layer and to first terminal, has a substantially equal lateral size to the p-type III-N layer. Central portion of light emitting region on first side and first metal layer includes first via that is etched through p-type portion, light emitting region and first part of n-type III-N portion. Second side of central portion of light emitting region that is opposite to first side includes second via connected to first via. Second via is etched through second part of n-type portion. First via includes second metal layer coupled to intersection between first and second vias. Electrically-insulating layer is coupled to first metal layer, first via, and second metal layer. First terminals are exposed from electrically-insulating layer. Third metal layer including second terminal is coupled to n-type portion on second side of light emitting region and to second metal layer through second via.

A light-emitting diode, a method of manufacturing the same, a lamp and an illumination device. A light-emitting diode (100) is provided with a compound semiconductor layer (10) including a light-emitting layer (24) provided on a substrate (1); an ohmic contact electrode (7) provided between the substrate and compound semiconductor layer; an ohmic electrode (11) provided on the side of the compound semiconductor layer opposite the substrate; a surface electrode (12) including a branch section (12b) provided so as to cover the surface of the ohmic electrode and a pad section (12a) coupled to the branch section; and a current-blocking portion (13) provided between an under-pad light-emitting layer (24a) arranged in an area of the light-emitting layer that overlaps the pad section (12a) and a light-emitting layer arranged in an area except the area that overlaps the pad section, to prevent current from being supplied to the under-pad light-emitting layer.

A lighting emitting diode including: an n side layer and a p side layer formed by nitride semiconductors respectively; an active layer comprising a nitride semiconductor is between the n side layer and the p side layer; wherein, the n-side layer is successively laminated by an extrinsically-doped buffer layer and a compound multi-current spreading layer; the compound multi-current spreading layer is successively-laminated by a first current spreading layer, a second current spreading layer and a third current spreading layer; the first current spreading layer and the third current spreading layer are alternatively-laminated layers comprising a u-type nitride semiconductor layer and an n-type nitride semiconductor layer; the second current spreading layer is a distributed insulation layer formed on the n-type nitride semiconductor layer; and the first current spreading layer is adjacent to the extrinsically-doped buffer layer; and the third current spreading layer is adjacent to the active layer.

Disclosed are a light emitting device and a light emitting device package. The light emitting device includes a light emitting structure including a first conductive semiconductor layer, an active layer on the first conductive semiconductor layer and a second conductive semiconductor layer on the active layer; a first electrode pad on the first conductive semiconductor layer; a second electrode pad on the second conductive semiconductor layer; and a current blocking pattern overlapping an edge of at least one of the first and second electrode pads.

A light emitting device, includes a substrate; a plurality of light emitting stacked layers, comprising a first surface and a second surface; a mesa structure; a current blocking (CB) layer; a transparent conductive layer; a first pad electrode and a second pad electrode; and a passivation layer, wherein the second surface is electrically opposite to the first surface, the transparent conductive layer is disposed on or above the first surface, the first pad electrode is disposed on the transparent conductive layer and on the first surface, and the second pad electrode is disposed on the second surface and on the mesa structure, the CB layer is disposed on the first surface, surrounded by the transparent conductive layer, and at a lower region of the first pad electrode, a portion of the first pad electrode is filling a first opening of the transparent conductive layer and the CB layer.