Various improvements in vertical transistors, such as IGBTs, are disclosed. The improvements include forming periodic highly-doped p-type emitter dots in the top surface region of a growth substrate, followed by growing the various transistor layers, followed by grounding down the bottom surface of the substrate, followed by a wet etch of the bottom surface to expose the heavily doped p+ layer. A metal contact is then formed over the p+ layer. In another improvement, edge termination structures utilize p-dopants implanted in trenches to create deep p-regions for shaping the electric field, and shallow p-regions between the trenches for rapidly removing holes after turn-off. In another improvement, a dual buffer layer using an n-layer and distributed n+ regions improves breakdown voltage and saturation voltage. In another improvement, p-zones of different concentrations in a termination structure are formed by varying pitches of trenches. In another improvement, beveled saw streets increase breakdown voltage.

Provided is a semiconductor device comprising: a semiconductor substrate; a plurality of gate trench sections formed in the semiconductor substrate; and a plurality of emitter trench sections formed in the semiconductor substrate, one or more emitter trench sections provided in each region between adjacent gate trench sections of the plurality of gate trench sections, wherein the semiconductor device includes at least one of: pairs of gate trench sections in which at least two gate trench sections of the plurality of gate trench sections are connected; and a pair of emitter trench sections in which at least two emitter trench sections of the plurality of emitter trench sections are connected.

A semiconductor device includes a semiconductor substrate comprising a main surface and a gate electrode in a trench between neighboring semiconductor mesas, The gate electrode is electrically insulated from the neighboring semiconductor mesas by a dielectric layer. The semiconductor device further includes a conductor arranged, at least partially, between neighboring dielectric contact spacers. The conductor has a conductivity greater than a conductivity of the gate electrode, An interface between the conductor and the gate electrode extends along the gate electrode.

In one embodiment, a power MOSFET cell includes an N+ silicon substrate having a drain electrode. An N-type drift layer is grown over the substrate. An N-type layer, having a higher dopant concentration than the drift region, is then formed along with a trench having sidewalls. A P-well is formed in the N-type layer, and an N+ source region is formed in the P-well. A gate is formed over the P-well's lateral channel and has a vertical extension into the trench. A positive gate voltage inverts the lateral channel and increases the vertical conduction along the sidewalls to reduce on-resistance. A vertical shield field plate is also located next to the sidewalls and may be connected to the gate. The field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage. A buried layer and sinker enable the use of a topside drain electrode.

In some aspects of the invention, an n-type field-stop layer can have a total impurity of such an extent that a depletion layer spreading in response to an application of a rated voltage stops inside the n-type field-stop layer together with the total impurity of an n.sup. type drift layer. Also, the n-type field-stop layer can have a concentration gradient such that the impurity concentration of the n-type field-stop layer decreases from a p.sup.+ type collector layer toward a p-type base layer, and the diffusion depth is 20 m or more. Furthermore, an n.sup.+ type buffer layer of which the peak impurity concentration can be higher than that of the n-type field-stop layer at 610.sup.15 cm.sup.3 or more, and one-tenth or less of the peak impurity concentration of the p.sup.+ type collector layer, can be included between the n-type field-stop layer and p.sup.+ type collector layer.

An improvement is achieved in the performance of a semiconductor device. The semiconductor device includes a first trench gate electrode and second and third trench gate electrodes located on both sides of the first trench gate electrode interposed therebetween. In each of a semiconductor layer located between the first and second trench gate electrodes and the semiconductor layer located between the first and third trench gate electrodes, a plurality of p.sup.+-type semiconductor regions are formed. The p.sup.+-type semiconductor regions are arranged along the extending direction of the first trench gate electrode in plan view to be spaced apart from each other.

The surface of an interlayer insulating film formed over an emitter coupling portion and the surface of an emitter electrode formed over the interlayer insulating film are caused to have a gentle shape, in particular, at the end of the emitter coupling portion, by forming the emitter coupling portion over a main surface of a semiconductor substrate and integrally with trench gate electrodes in order to form a spacer over the sidewall of the emitter coupling portion. Thereby, stress is dispersed, not concentrated in an acute angle portion of the emitter coupling portion when an emitter wire is coupled to the emitter electrode (emitter pad), and hence occurrence of a crack can be suppressed. Further, by forming the spacer, the concavities and convexities to be formed in the surface of the emitter electrode can be reduced, whereby the adhesiveness between the emitter electrode and the emitter wire can be improved.

Provided is a semiconductor device, including: a semiconductor substrate including a bulk donor; an active portion provided on the semiconductor substrate; and an edge termination structure portion provided between the active portion and an end side of the semiconductor substrate on a upper surface of the semiconductor substrate; wherein the active portion includes hydrogen, and has a first high concentration region with a higher donor concentration than a bulk donor concentration; and the edge termination structure portion, which is provided in a range that is wider than the first high concentration region in a depth direction of the semiconductor substrate, includes hydrogen, and has a second high concentration region with a higher donor concentration than the bulk donor concentration.

In one embodiment, an IGBT is formed to include a region of semiconductor material. Insulated gate structures are disposed in region of semiconductor material extending from a first major surface. An n-type field stop region extends from a second major surface into the region of semiconductor material. A p+ type polycrystalline semiconductor layer is disposed adjacent to the field stop region and provides an emitter region for the IGBT. An embodiment may include a portion of the p+ type polycrystalline semiconductor being doped n-type.

A semiconductor structure includes a semiconductor substrate having a gate electrode in a gate trench, a buried bus in the semiconductor substrate, the buried bus having a bus conductive filler in a bus trench, where the bus conductive filler is electrically coupled to the gate electrode. The bus conductive filler is surrounded by the gate electrode. The gate trench intersects the bus trench in the semiconductor substrate. The gate electrode includes polysilicon. The bus conductive filler includes tungsten. The semiconductor structure also includes an adhesion promotion layer interposed between the bus conductive filler and the gate electrode, where the adhesion promotion layer includes titanium and titanium nitride. The semiconductor structure also includes a dielectric layer covering the gate electrode over the semiconductor substrate, where the buried bus has a coplanar top surface with the dielectric layer.