A semiconductor device according to an embodiment includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, a fourth semiconductor layer of the second conductivity type, a first electrode connected to the second semiconductor layer and the fourth semiconductor layer, a second electrode facing the second semiconductor layer with an insulating film interposed, a fifth semiconductor layer of the second conductivity type, a sixth semiconductor layer of the first conductivity type, a seventh semiconductor layer of the second conductivity type, a third electrode connected to the fifth semiconductor layer and the seventh semiconductor layer, and a fourth electrode facing the fifth semiconductor layer with an insulating film interposed.

A method of manufacturing a semiconductor device includes a semiconductor region forming process, a cleaning process, a surface roughness uniformizing process, and an electrode forming process. As the semiconductor region forming process, semiconductor regions are formed such that a plurality of semiconductor regions with different ion injection amounts are exposed on one principal surface of a semiconductor substrate. As the cleaning process, after the semiconductor region forming process, a cleaning using hydrofluoric acid is performed on the one principal surface of the semiconductor substrate. As the surface roughness uniformizing process, after the cleaning process, the surface roughness of the one principal surface of the semiconductor substrate is uniformized. As the electrode forming process, after the surface roughness uniformizing process, electrodes are formed on the one principal surface of the semiconductor substrate.

A semiconductor device includes a plurality of gate electrodes. Each gate electrode includes a first portion extending from a first end to a second end and a second portion extending parallel the first portion from a first end to a second end. The first and second portions are spaced from each other. A third portion of at least one gate electrode connects the first end of the first portion to the first end of the second portion of the gate electrode. A first insulating film is on the plurality of gate electrodes. A first interconnect portion is disposed on the first or second portion the gate electrode to electrically connecting the gate electrode to a gate pad. A second interconnect portion is disposed on semiconductor regions between the gate electrodes and electrically connects the semiconductor regions to an emitter pad.

A semiconductor device includes an interlayer insulating film in which first contact holes and second contact holes are provided. Each of the second contact holes has a width narrower than a width of the corresponding first contact hole. A contact plug is located in the corresponding second contact hole. An upper electrode layer is arranged on an upper surface of the interlayer insulating film, upper surfaces of the contact plugs, and inner surfaces of the first contact holes. The protective insulating film covers an upper surface of the external field. An end portion extending along a direction intersecting with the plurality of trenches of the protective insulating film extends through a range located above the plurality of the second contact holes. A pillar region is in contact with the upper electrode layer in the first contact hole.

An insulated gate bipolar transistor (IGBT) includes a gate trench, an emitter trench, and an electrically insulative layer coupled to the emitter trench and the gate trench and electrically isolating the gate trench from an electrically conductive layer. A contact opening in the electrically insulative layer extends into the emitter trench and the electrically conductive layer electrically couples with the emitter trench therethrough. A P surface doped (PSD) region and an N surface doped (NSD) region are each located between the electrically conductive layer and a plurality of semiconductor layers of the IGBT and between the gate trench and the emitter trench. The electrically conductive layer electrically couples to the plurality of semiconductor layers through the PSD region and/or the NSD region.

A termination structure of a semiconductor device is provided. The semiconductor device includes an active area and a termination area adjacent to the active area, in which the termination area has the termination structure. The termination structure includes a substrate, an epitaxy layer, a dielectric layer, a conductive material layer and a conductive layer. The epitaxy layer is disposed on the substrate and has a voltage-sustaining region. The voltage-sustaining region has trenches parallel to each other. The dielectric layer is disposed in the trenches and on a portion of the epitaxy layer. The conductive material layer is disposed on the dielectric layer in the trenches. The conductive layer covers the trenches, and is in contact with the conductive material layer and a portion of the epitaxy layer, and is electrically connected between the active area and the termination area. A method for manufacturing the termination structure is also provided.

There are disclosed herein various implementations of a latch-up free power transistor. Such a device includes an insulated gate situated adjacent to a conduction channel in the power transistor, an emitter electrode in direct physical contact with the conduction channel, and a collector electrode in electrical contact with the conduction channel. The power transistor also includes an emitter layer in contact with a surface of a semiconductor substrate adjacent the conduction channel.

Disclosed herein is a shielded-gate silicon carbide trench MOS-controlled switch, such as a MOSFET or IGBT, with a reduced Miller capacitance. The switch disclosed herein can be used in a variety of applications, including high temperature and/or high voltage power conversion.

A semiconductor device includes a plurality of gate electrodes. Each gate electrode includes a first portion extending from a first end to a second end and a second portion extending parallel the first portion from a first end to a second end. The first and second portions are spaced from each other. A third portion of at least one gate electrode connects the first end of the first portion to the first end of the second portion of the gate electrode. A first insulating film is on the plurality of gate electrodes. A first interconnect portion is disposed on the first or second portion the gate electrode to electrically connecting the gate electrode to a gate pad. A second interconnect portion is disposed on semiconductor regions between the gate electrodes and electrically connects the semiconductor regions to an emitter pad.

Provided is a semiconductor device comprising a semiconductor substrate having an upper surface and a lower surface, with a bulk donor distributed between the upper surface and the lower surface, that has a drift region of a first conductivity type provided thereon, the semiconductor device comprising a high-concentration region of a first conductivity type that is arranged between the drift region and the lower surface of the semiconductor substrate, includes a hydrogen donor, and has a carrier concentration that is higher than a bulk donor concentration, wherein the high-concentration region has a first portion in which a hydrogen donor concentration obtained by subtracting a bulk donor concentration from a carrier concentration is 710.sup.13/cm.sup.3 or more and 1.510.sup.14/cm.sup.3 or less, and a length of the first portion in a depth direction of the semiconductor substrate is 50% or more of a length of the high-concentration region.