Patent classifications
H10F77/14
Microstructure enhanced absorption photosensitive devices
Techniques for enhancing the absorption of photons in semiconductors with the use of microstructures are described. The microstructures, such as pillars and/or holes, effectively increase the effective absorption length resulting in a greater absorption of the photons. Using microstructures for absorption enhancement for silicon photodiodes and silicon avalanche photodiodes can result in bandwidths in excess of 10 Gb/s at photons with wavelengths of 850 nm, and with quantum efficiencies of approximately 90% or more.
Microstructure enhanced absorption photosensitive devices
Techniques for enhancing the absorption of photons in semiconductors with the use of microstructures are described. The microstructures, such as pillars and/or holes, effectively increase the effective absorption length resulting in a greater absorption of the photons. Using microstructures for absorption enhancement for silicon photodiodes and silicon avalanche photodiodes can result in bandwidths in excess of 10 Gb/s at photons with wavelengths of 850 nm, and with quantum efficiencies of approximately 90% or more.
MONOLITHIC INTEGRATION TECHNIQUES FOR FABRICATING PHOTODETECTORS WITH TRANSISTORS ON SAME SUBSTRATE
Examples of the various techniques introduced here include, but not limited to, a mesa height adjustment approach during shallow trench isolation formation, a transistor via first approach, and a multiple absorption layer approach. As described further below, the techniques introduced herein include a variety of aspects that can individually and/or collectively resolve or mitigate one or more traditional limitations involved with manufacturing PDs and transistors on the same substrate, such as above discussed reliability, performance, and process temperature issues.
Strain engineered bandgaps
An optoelectronic device as well as its methods of use and manufacture are disclosed. In one embodiment, the optoelectronic device includes a first optoelectronic material that is inhomogeneously strained. A first charge carrier collector and a second charge carrier collector are each in electrical communication with the first optoelectronic material and are adapted to collect charge carriers from the first optoelectronic material. In another embodiment, a method of photocatalyzing a reaction includes using a strained optoelectronic material.
MONOLITHIC INTEGRATION TECHNIQUES FOR FABRICATING PHOTODETECTORS WITH TRANSISTORS ON SAME SUBSTRATE
Examples of the various techniques introduced here include, but not limited to, a mesa height adjustment approach during shallow trench isolation formation, a transistor via first approach, and a multiple absorption layer approach. As described further below, the techniques introduced herein include a variety of aspects that can individually and/or collectively resolve or mitigate one or more traditional limitations involved with manufacturing PDs and transistors on the same substrate, such as above discussed reliability, performance, and process temperature issues.
SOLAR CELL STRUCTURES FOR IMPROVED CURRENT GENERATION AND COLLECTION
In one aspect, optoelectronic devices are described herein. In some implementations, an optoelectronic device comprises a photovoltaic cell. The photovoltaic cell comprises a space-charge region, a quasi-neutral region, and a low bandgap absorber region (LBAR) layer or an improved transport (IT) layer at least partially positioned in the quasi-neutral region of the cell.
SENSOR AND SENSOR SYSTEM
According to one embodiment, a sensor includes a first light-emitting region, a second light-emitting region, and a light receiving element. At least one of at least a portion of a first light or at least a portion of a second light is incident on the light receiving element. The first light is emitted from the first light-emitting region. The second light is emitted from the second light-emitting region. A second position of the second light-emitting region in a first direction is between a first position of the first light-emitting region in the first direction and a light receiving position of the light receiving element in the first direction. The first direction is from the first light-emitting region toward the second light-emitting region.
Laterally varying II-VI alloys and uses thereof
Described herein are semiconductor structures comprising laterally varying II-VI alloy layer formed over a surface of a substrate. Further, methods are provided for preparing laterally varying II-VI alloy layers over at least a portion of a surface of a substrate comprising contacting at least a portion of a surface of a substrate within a reaction zone with a chemical vapor under suitable reaction conditions to form a laterally varying II-VI alloy layer over the portion of the surface of the substrate, wherein the chemical vapor is generated by heating at least two II-VI binary compounds; and the reaction zone has a temperature gradient of at least 50-100 C. along an extent of the reaction zone. Also described here are devices such as lasers, light emitting diodes, detectors, or solar cells that can use such semiconductor structures. In the case of lasers, spatially varying wavelength can be realized while in the case of solar cells and detectors multiple solar cells can be achieved laterally where each cell absorbs solar energy of a given wavelength range such that entire solar spectrum can be covered by the said solar cell structure. For LED applications, spatial variation of alloy composition can be used to engineer colors of light emission.
Systems and methods for advanced ultra-high-performance InP solar cells
Systems and Methods for Advanced Ultra-High-Performance InP Solar Cells are provided. In one embodiment, an InP photovoltaic device comprises: a p-n junction absorber layer comprising at least one InP layer; a front surface confinement layer; and a back surface confinement layer; wherein either the front surface confinement layer or the back surface confinement layer forms part of a High-Low (HL) doping architecture; and wherein either the front surface confinement layer or the back surface confinement layer forms part of a heterointerface system architecture.
MEMS DEVICE AND FABRICATION METHOD THEREOF
A method for fabricating an MEMS device includes providing a first substrate with a central region and a peripheral region, and forming a plurality of first openings in the peripheral region and a plurality of third openings in the central region by etching the first substrate from a front side. The depth of the first openings is larger than the depth of the third openings. The method further includes forming a photosensitive layer on the surfaces of the first openings and the third openings, bonding a second substrate to the front side of the first substrate, and forming a trench by etching the first substrate from a back side using a patterned mask layer as an etch mask. The trench has a concave bottom surface and exposes a portion of the photosensitive layer formed on the bottom surfaces of the first openings and the third openings.