The disclosure relates to the technical field of solar cells, and provides a solar cell and a doped region structure thereof, a cell assembly, and a photovoltaic system. The doped region structure includes a first doped layer, a passivation layer, and a second doped layer that are disposed on a silicon substrate in sequence. The passivation layer is a porous structure having the first doped layer and/or the second doped layer inlaid in a hole region. The first doped layer and the second doped layer have a same doping polarity. By means of the doped region structure of the solar cell provided in the disclosure, the difficulty in production and the limitation on conversion efficiency as a result of precise requirements for the accuracy of a thickness of a conventional tunneling layer are resolved.

A Ge-on-Si photodetector constructed without doping or contacting Germanium by metal is described. Despite the simplified fabrication process, the device has responsivity of 1.24 A/W, corresponding to 99.2% quantum efficiency. Dark current is 40 nA at 4 V reverse bias. 3-dB bandwidth is 30 GHz.

Various embodiment include optical and optoelectronic devices and methods of making same. Under one aspect, an optical device includes an integrated circuit having an array of conductive regions, and an optically sensitive material over at least a portion of the integrated circuit and in electrical communication with at least one conductive region of the array of conductive regions. Under another aspect, a film includes a network of fused nanocrystals, the nanocrystals having a core and an outer surface, wherein the core of at least a portion of the fused nanocrystals is in direct physical contact and electrical communication with the core of at least one adjacent fused nanocrystal, and wherein the film has substantially no defect states in the regions where the cores of the nanocrystals are fused. Additional devices and methods are described.

Various particular embodiments include a method for forming a photodetector, including: forming a structure including a barrier layer disposed between a layer of doped silicon (Si) and a layer of germanium (Ge), the barrier layer including a crystallization window; and annealing the structure to convert, via the crystallization window, the Ge to a first composition of silicon germanium (SiGe) and the doped Si to a second composition of SiGe.

Channel stop sections formed by multiple times of impurity ion implanting processes. Four-layer impurity regions are formed across the depth of a semiconductor substrate (across the depth of the bulk), so that a P-type impurity region is formed deep in the semiconductor substrate; thus, incorrect movement of electric charges is prevented. Other four-layer impurity regions of another channel stop section are decreased in width step by step across the depth of the substrate, so that the reduction of a charge storage region of a light receiving section due to the dispersion of P-type impurity in the channel stop section is prevented in the depth of the substrate.

An optical apparatus includes a substrate 1, a wiring pattern 8 formed on the substrate 1, a light-receiving element 3 and a light-emitting element 2 provided on the substrate 1 and spaced apart from each other in a direction x, a light-transmitting resin 4 covering the light-receiving element 3, a light-transmitting resin 5 covering the light-emitting element 2, and a light-shielding resin 6 covering the light-transmitting resin 4 and the light-transmitting resin 5. The wiring pattern 8 includes a first light-blocking portion 83 interposed between the light-shielding resin 6 and the substrate 1 and positioned between the light-receiving element 3 and the light-emitting element 2 as viewed in x-y plane. The first light-blocking portion 83 extends across the light-emitting element 2 as viewed in the direction x.

Provided are a nanostructure and an optical device including the nanostructure. The nanostructure is formed on a two-dimensional material layer such as graphene and includes nanopatterns having different shapes. The nanopatterns may include a first nanopattern and a second nanopattern and may be spherical; cube-shaped; or poly-pyramid-shaped, including a triangular pyramid shape; or polygonal pillar-shaped.

A SPAD including, in a substrate of a first conductivity type: a first region of the second conductivity type extending from the upper surface of the substrate; a second region of the first type of greater doping level than the substrate, extending from the lower surface of the first region, having a surface area smaller than that of the first region and being located opposite a central portion of the first region; a third region of the first type of greater doping level than the substrate extending from the upper surface of the substrate, laterally surrounding the first region; and a fourth buried region of the first type of greater doping level than the substrate, forming a peripheral ring connecting the second region to the third region.

Backside illuminated photosensitive devices and associated methods are provided. In one aspect, for example, a backside-illuminated photosensitive imager device can include a semiconductor substrate having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation, and a passivation region positioned between the textured region and the at least one junction. The passivation region is positioned to isolate the at least one junction from the textured region, and the semiconductor substrate and the textured region are positioned such that incoming electromagnetic radiation to passes through the semiconductor substrate before contacting the textured region.

Additionally, the device includes an electrical transfer element coupled to the semiconductor substrate to transfer an electrical signal from the at least one junction.

Some embodiments of vacuum electronics call for nanoscale field-enhancing geometries. Methods and apparatus for using nanoparticles to fabricate nanoscale field-enhancing geometries are described herein. Other embodiments of vacuum electronics call for methods of controlling spacing between a control grid and an electrode on a nano- or micron-scale, and such methods are described herein.