Patent classifications
H10H20/8215
Heterostructure including a semiconductor layer with graded composition
An improved heterostructure for an optoelectronic device is provided. The heterostructure includes an active region, an electron blocking layer, and a p-type contact layer. The heterostructure can include a p-type interlayer located between the electron blocking layer and the p-type contact layer. In an embodiment, the electron blocking layer can have a region of graded transition. The p-type interlayer can also include a region of graded transition.
Solid state lighting devices with dielectric insulation and methods of manufacturing
Semiconductor lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a semiconductor lighting device includes a first semiconductor material, a second semiconductor material spaced apart from the first semiconductor material, and an active region between the first and second semiconductor materials. The semiconductor lighting device also includes an indentation extending from the second semiconductor material toward the active region and the first semiconductor material and an insulating material in the indentation of the solid state lighting structure.
LIGHT-EMITTING DIODE EPITAXIAL STRUCTURE AND LIGHT-EMITTING DIODE
A light-emitting diode epitaxial structure and a light-emitting diode are provided. The light-emitting diode epitaxial structure is provided with an Mg modulation layer disposed between a multi-quantum well light-emitting layer and a first hole injection layer. The average impurity doping concentration of the Mg modulation layer is A, the average impurity doping concentration of the first hole injection layer is B, and the average impurity doping concentration of an electron blocking layer is C, where B>A>C.
Device Including a Semiconductor Layer With Graded Composition
An improved heterostructure for an optoelectronic device is provided. The heterostructure includes an active region, an electron blocking layer, and a p-type contact layer. The heterostructure can include a p-type interlayer located between the electron blocking layer and the p-type contact layer. In an embodiment, the electron blocking layer can have a region of graded transition. The p-type interlayer can also include a region of graded transition.
Optoelectronic semiconductor chip and method for producing optoelectronic semiconductor chips
In an embodiment an optoelectronic semiconductor chip includes a semiconductor layer sequence including a first semiconductor region of a first conductivity type, an active zone having a multiple quantum well structure composed of a plurality of quantum well layers and barrier layers, a second semiconductor region of a second conductivity type and a plurality of channels extending through the active zone, wherein the second semiconductor region is located in the channels and is configured for lateral current injection into the active zone, wherein the channels have a first aperture half-angle in the first semiconductor region and a second aperture half-angle in the active zone, and wherein the second aperture half-angle is greater than zero and less than the first aperture half-angle.
Light-emitting diode comprising a hybrid structure formed of layers and nanowire
A light-emitting diode is provided, including: a first layer of n-doped Al.sub.X1Ga.sub.(1-X1-Y1)In.sub.Y1N, with X1>0 and X1+Y11; a second layer of p-doped Al.sub.X2Ga.sub.(1-X2-Y2)In.sub.Y2N, with X2>0 and X2+Y21; an active area disposed between the first and the second layers and comprising at least one multi-quantum well emissive structure; nanowires based on AlN p-doped with indium and magnesium atoms, disposed on the second layer; and an ohmic contact layer in contact with the nanowires. A method for producing a light-emitting diode is also provided.
LIGHT SOURCE MODULE
Provided a light source module in which ultraviolet light extraction efficiency is enhanced and stress that occurs to a light emitting element is reduced even if an area ratio of the light emitting element to a mounting substrate is large. The light source module includes a plurality of light emitting elements formed of a semiconductor and configured to emit ultraviolet light to sterilize a fluid, a mounting substrate having the plurality of light emitting elements mounted thereon, a light transmitting member transmitting the ultraviolet light and separating the plurality of light emitting elements and the mounting substrate from the fluid, and a liquid substance filled in a gap surrounded by an outer surface of the plurality of light emitting elements, the mounting substrate, and the light transmitting member.
Method for electrochemically etching a semiconductor structure
A method for etching a semiconductor structure (110) is provided, the semiconductor structure comprising a sub-surface quantum structure (30) of a first III-V semiconductor material, beneath a surface layer (31) of a second III-V semiconductor material having a charge carrier density of less than 510.sup.17 cm.sup.3. The sub-surface quantum structure may comprise, for example, a quantum well, or a quantum wire, or a quantum dot. The method comprises the steps of exposing the surface layer to an electrolyte (130), and applying a potential difference between the first III-V semiconductor material and the electrolyte, to electrochemically etch the sub-surface quantum structure (30) to form a plurality of nanostructures, while the surface layer (31) is not etched. A semiconductor structure, uses thereof, and devices incorporating such semiconductor structures are further provided.
LIGHT EMITTING DEVICE
A light emitting device according to an embodiment of the present disclosure includes: a first electrically-conductive layer (10) that is of a first electrically-conductive type; a first high resistance part (51) that is provided in the first electrically-conductive layer (10) and that includes first atoms; a second electrically-conductive layer (20) that is of a second electrically-conductive type; a second high resistance part (52) that is provided in the second electrically-conductive layer (20) and that includes second atoms; and an active layer (30) that is provided between the first electrically-conductive layer (10) and the second electrically-conductive layer (20). A concentration of the first atoms inside the first high resistance part (51) is greater than a concentration of the first atoms in a first surface (11S1) of the first electrically-conductive layer (10).
n-Type GaN crystal, GaN wafer, and GaN crystal, GaN wafer and nitride semiconductor device production method
Provided is an n-type GaN crystal, in which a donor impurity contained at the highest concentration is Ge, and which has a room-temperature resistivity of lower than 0.03 .Math.cm and a (004) XRD rocking curve FWHM of less than 20 arcsec. The n-type GaN crystal has two main surfaces, each having an area of 3 cm.sup.2 or larger. One of the two main surfaces can have a Ga polarity and can be inclined at an angle of 0 to 10 with respect to a (0001) crystal plane. Further, the n-type GaN crystal can have a diameter of 20 mm or larger.