Embodiments of the present invention include a method for manufacturing, and a structure for a thin film solar module. The method of manufacturing includes fabricating a thin film solar cell and fabricating an electronic conversion unit (ECU) on a single substrate. The thin film solar cell has at least one solar cell diode on a substrate. The ECU has at least one transistor on the substrate. The ECU may further comprise a capacitor and an inductor. The ECU is integrated on the substrate monolithically and electrically connected with the thin film solar cell. The ECU and the thin film solar cell interconnect to form a circuit on the substrate. The ECU is electrically connected to a microcontroller on the solar cell module.

The present technology relates to multi-cell devices fabricated on a common substrate that are more desirable than single cell devices, particularly in photovoltaic applications. Multi-cell devices operate with lower currents, higher output voltages, and lower internal power losses. Prior art multi-cell devices use physical isolation to achieve electrical isolation between cells. In order to fabricate a multicell device on a common substrate, the individual cells must be electrically isolated from one another. In the prior art, isolation generally required creating a physical dielectric barrier between the cells, which adds complexity and cost to the fabrication process. The disclosed technology achieves electrical isolation without physical isolation by proper orientation of interdigitated junctions such that the diffusion fields present in the interdigitated region essentially prevent the formation of a significant parasitic current which would be in opposition to the output of the device.

A method including providing a substrate comprising a device layer on which a plurality of device cells are defined; depositing a first dielectric layer on the device layer and metal interconnect such that the deposited interconnect is electrically connected to at least two of the device cells; depositing a second dielectric layer over the interconnect; and exposing at least one contact point on the interconnect through the second dielectric layer. An apparatus including a substrate having defined thereon a device layer including a plurality of device cells; a first dielectric layer disposed directly on the device layer; a plurality of metal interconnects, each of which is electrically connected to at least two of the device cells; and a second dielectric layer disposed over the first dielectric layer and over the interconnects, wherein the second dielectric layer is patterned in a positive or negative planar spring pattern.

Intercalation pastes for use with semiconductor devices are disclosed. The pastes contain precious metal particles, intercalating particles, and an organic vehicle and can be used to improve the material properties of metal particle layers. Specific formulations have been developed to be screen-printed directly onto a dried metal particle layer and fired to make a fired multilayer stack. The fired multilayer stack can be tailored to create a solderable surface, high mechanical strength, and low contact resistance. In some embodiments, the fired multilayer stack can etch through a dielectric layer to improve adhesion to a substrate. Such pastes can be used to increase the efficiency of silicon solar cells, specifically multi- and mono-crystalline silicon back-surface field (BSF), and passivated emitter and rear contact (PERC) photovoltaic cells. Other applications include integrated circuits and more broadly, electronic devices.

In accordance with embodiments disclosed herein, there are provided methods and systems for implementing damage-and-resist-free laser patterning of dielectric films on textured silicon. For example, in one embodiment, such means include means for depositing a Silicon nitride (SiNx) or SiOx (silicon oxide) layer onto a crystalline silicon (c-Si) substrate by a Plasma Enhanced Chemical Vapor Deposition (PECVD) processing; depositing an amorphous silicon (a-Si) film on top of the SiNx or SiOx layer; patterning the a-Si film to define an etch mask for the SiNx or SiOx layer; removing the SiNx or SiOx layer via a Buffered Oxide Etch (BOE) chemical etch to expose the c-Si surface; removing the a-Si mask with a hydrogen plasma etch in a PECVD tool to prevent current loss from the mask; and plating the exposed c-Si surface with metal contacts. Other related embodiments are disclosed.

After forming an absorber layer containing cracks over a back contact layer, a passivation layer is formed over a top surface of the absorber layer and interior surfaces of the cracks. The passivation layer is deposited in a manner such that that the cracks in the absorber layer are fully passivated by the passivation layer. An emitter layer is then formed over the passivation layer to pinch off upper portions of the cracks, leaving voids in lower portions of the cracks.

Methods of fabricating solar cell emitter regions with differentiated P-type and N-type regions architectures, and resulting solar cells, are described. In an example, a back contact solar cell includes a substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region of a first conductivity type is disposed on a first thin dielectric layer disposed on the back surface of the substrate. A second polycrystalline silicon emitter region of a second, different, conductivity type is disposed on a second thin dielectric layer disposed on the back surface of the substrate. A third thin dielectric layer is disposed laterally directly between the first and second polycrystalline silicon emitter regions. A first conductive contact structure is disposed on the first polycrystalline silicon emitter region. A second conductive contact structure is disposed on the second polycrystalline silicon emitter region.

Approaches for the foil-based metallization of solar cells and the resulting solar cells are described. In an example, a solar cell includes a substrate. A plurality of alternating N-type and P-type semiconductor regions is disposed in or above the substrate. A conductive contact structure is disposed above the plurality of alternating N-type and P-type semiconductor regions. The conductive contact structure includes a plurality of metal seed material regions providing a metal seed material region disposed on each of the alternating N-type and P-type semiconductor regions. A metal foil is disposed on the plurality of metal seed material regions, the metal foil having anodized portions isolating metal regions of the metal foil corresponding to the alternating N-type and P-type semiconductor regions.

Methods of fabricating solar cells using a metal-containing thermal and diffusion barrier layer in foil-based metallization approaches, and the resulting solar cells, are described. For example, a method of fabricating a solar cell includes forming a plurality of semiconductor regions in or above a substrate. The method also includes forming a metal-containing thermal and diffusion barrier layer above the plurality of semiconductor regions. The method also includes forming a metal seed layer on the metal-containing thermal and diffusion barrier layer. The method also includes forming a metal conductor layer on the metal seed layer. The method also includes laser welding the metal conductor layer to the metal seed layer. The metal-containing thermal and diffusion barrier layer protects the plurality of semiconductor regions during the laser welding.

Approaches for forming solar cells with a converted seed layer as a buffer material and the resulting solar cells are described. In an example, a method of fabricating a solar cell includes converting regions of a seed layer disposed on a plurality of p-n junctions of the solar cell to form a pattern of interdigitated converted regions. The converted regions are configured to electrically insulate non-converted regions of the seed layer from each other and provide a barrier to a laser that is, in fabricating the solar cell, directed towards the seed layer such that the barrier substantially avoids degradation of at least the plurality of p-n junctions from the laser.