An integrated circuit and method of forming the integrated circuit, including the steps of forming channels partially into a thickness of a semiconductor layer or through the thickness of the semiconductor layer and partially through a thickness of a substrate layer on which the semiconductor layer was formed. The method may then include underfilling or overfilling the channels with diamond. If underfilled, a remainder of the channels may be filled in with nucleation buffer layers or additional semiconductor material. If overfilled, the diamond may be selectively polished down to form a planar surface with the semiconductor layer. Next, the method may include forming an active device layer over the semiconductor material and diamond. The method may also include thinning the substrate layer down to the diamond and then placing a heat sink in physical contact with the diamond in the channel.

The present invention relates generally to high current density access devices (ADs), and more particularly, to a structure and method of forming tunable voltage margin access diodes in phase change memory (PCM) blocks using layers of copper-containing mixed ionic-electronic conduction (MIEC) materials. Embodiments of the present invention may use layers MIEC material to form an access device that can supply high current-densities and operate reliably while being fabricated at temperatures that are compatible with standard BEOL processing. By varying the deposition technique and amount of MIEC material used, the voltage margin (i.e. the voltage at which the device turns on and the current is above the noise floor) of the access device may be tuned to specific operating conditions of different memory devices.

The present invention relates to the inspection process which includes providing access to the microdevice contacts, measuring the microdevice and analyzing the data to identify defects or performance of the micro device. The invention also relates to the forming of test electrodes on microdevices. The test electrodes may be connected to hidden contacts. The type of microdevices may be vertical, lateral or a flip chip.

A semiconductor structure includes a substrate; and a graded III-V layer over the substrate. The semiconductor structure further includes a p-doped gallium nitride (GaN) layer over the graded III-V layer. The semiconductor structure further includes one or more sets of GaN layers over the p-doped GaN layer. Each set of the one or more sets of GaN layers includes a lower GaN layer, wherein the lower GaN layer is undoped, unintentionally doped having N-type doping, or N-type doped. Each set of the one or more sets of GaN layers includes an upper GaN layer on the lower GaN layer, wherein the upper GaN layer is P-type doped. The semiconductor structure includes a second GaN layer over the one or more sets of GaN layers, the second GaN layer being either undoped or unintentionally doped having the N-type doping. The semiconductor structure includes an active layer over the second GaN layer.

A structure includes a substrate and a strain relaxed buffer (SRB) that has a bottom surface disposed on the substrate and an opposite top surface. The SRB is formed to have a plurality of pairs of layers, where a given pair of layers is composed of a layer of Si.sub.1-xGe.sub.x and a layer of Si. The structure further includes a plurality of transistor devices formed above the top surface of the SRB and at least one contact disposed vertically through the top surface of the SRB and partially through a thickness of the SRB. The at least one contact is thermally coupled to at least one of the plurality of the Si layers for conducting heat out of the SRB via the at least one of the plurality of Si layers. A method to form the structure is also disclosed.

There are disclosed herein various implementations of a semiconductor structure and method. The semiconductor structure comprises a substrate, a transition body over the substrate, and a group III-V intermediate body having a bottom surface over the transition body. The semiconductor structure also includes a group III-V device layer over a top surface of the group III-V intermediate body. The group III-V intermediate body has a continuously reduced impurity concentration wherein a higher impurity concentration at the bottom surface is continuously reduced to a lower impurity concentration at the top surface.

The present invention relates generally to high current density access devices (ADs), and more particularly, to a structure and method of forming tunable voltage margin access diodes in phase change memory (PCM) blocks using layers of copper-containing mixed ionic-electronic conduction (MIEC) materials. Embodiments of the present invention may use layers MIEC material to form an access device that can supply high current-densities and operate reliably while being fabricated at temperatures that are compatible with standard BEOL processing. By varying the deposition technique and amount of MIEC material used, the voltage margin (i.e. the voltage at which the device turns on and the current is above the noise floor) of the access device may be tuned to specific operating conditions of different memory devices.

A structure includes a substrate and a strain relaxed buffer (SRB) that has a bottom surface disposed on the substrate and an opposite top surface. The SRB is formed to have a plurality of pairs of layers, where a given pair of layers is composed of a layer of Si.sub.1-xGe.sub.x and a layer of Si. The structure further includes a plurality of transistor devices formed above the top surface of the SRB and at least one contact disposed vertically through the top surface of the SRB and partially through a thickness of the SRB. The at least one contact is thermally coupled to at least one of the plurality of the Si layers for conducting heat out of the SRB via the at least one of the plurality of Si layers. A method to form the structure is also disclosed.

A superjunction bipolar transistor includes an active transistor cell area that includes active transistor cells electrically connected to a first load electrode at a front side of a semiconductor body. A superjunction area overlaps the active transistor cell area and includes a low-resistive region and a reservoir region outside of the low-resistive region. The low-resistive region includes a first superjunction structure with a first vertical extension with respect to a first surface of the semiconductor body. The reservoir region includes no superjunction structure or a second superjunction structure with a mean second vertical extension smaller than the first vertical extension.

A high electron mobility transistor comprises a substrate, an epitaxial stack arranged above the substrate and having a first region and a second region surrounding the first region, a matrix electrode structure arranged in the first region. The matrix electrode comprises a plurality of first electrodes arranged on the epitaxial stack, a plurality of second electrodes arranged on the epitaxial stack and adjacent to the plurality of first electrodes, a plurality of third electrodes arranged adjacent to the plurality of first electrodes and second electrodes. One of the plurality of first electrodes comprises a first side, a second side, a third side and a fourth side. The first side and the third side are opposite sides, and the second side and the fourth side are opposite sides. Two of the plurality of second electrodes are arranged on the first side and the third side, and two of the plurality of third electrodes are arranged on the second side and the fourth side.