The present disclosure provides a display substrate, a manufacturing method thereof, and a display device. The display substrate comprises a base substrate, and a first thin film transistor and a second thin film transistor formed on the base substrate, wherein a first active layer of the first thin film transistor is made of low-temperature polysilicon, and a second active layer of the second thin film transistor is made of a metal oxide. The display substrate further comprises a first barrier layer on a side of the second active layer close to the base substrate and a second barrier layer on a side of the second active layer away from the base substrate. The orthographic projection of the second active layer onto the base substrate falls within the orthographic projections of the first barrier layer and the second barrier layer onto the base substrate.

A semiconductor device and methods for forming the semiconductor device are described. The semiconductor device can include a top transistor and a bottom transistor arranged in a stack configuration, and an isolation layer situated between the top transistor and the bottom transistor. The top transistor can be encompassed by a high-k gate dielectric. The bottom transistor can be encompassed by a metal-doped high-k gate dielectric. A first portion of the isolation layer can be encompassed by the high-k gate dielectric. A second portion of the isolation layer can be encompassed by the metal-doped high-k gate dielectric. The metal-doped high-k gate dielectric can encompass the bottom transistor and the second portion of the isolation layer can be encompassed by a layer of first work function material (WFM). The first WFM can be encompassed by a second WFM.

A display apparatus includes an oxide semiconductor pattern disposed on a device substrate and including a channel region disposed between a source region and a drain region, a gate electrode overlapping the channel region of the oxide semiconductor pattern and having a structure in which a first hydrogen barrier layer and a gate conductive layer are stacked, and a gate insulating film disposed between the oxide semiconductor pattern and the gate electrode to expose the source region and the drain region of the oxide semiconductor pattern. The gate electrode exposes a portion of the gate insulating film that is adjacent to the source region and a portion of the gate insulating film that is adjacent to the drain region.

The present application provides a display panel and a display device. The display panel includes a substrate, a gate electrode, an insulating barrier layer, and an active layer. The active layer is disposed on a side of the gate electrode away from or close to the substrate, and the insulating barrier layer is disposed between the gate electrode and the active layer; wherein band gap widths of materials of the insulating barrier layer are greater than a work function of a material of the gate electrode.

An electronic device is provided. The electronic device includes a substrate, a first active layer, a second active layer, a first gate electrode, a first insulator, a second gate electrode, a second insulator, a first electrode electrically connected to the second active layer, and a second electrode. The first active layer is different from the second active layer in material. The first insulator is disposed between the first active layer and the first gate electrode. The second insulator is disposed between the second active layer and the second gate electrode. The second gate electrode is disposed between the first electrode and the second active layer. The second electrode is overlapped with at least part of the second active layer. The second electrode and the first gate electrode are the same in material.

An organic light-emitting display device includes a driving transistor configured to control current to an organic light-emitting diode from a power voltage line, a compensation transistor configured to diode-connect the driving transistor in response to a voltage applied to a compensation gate electrode of the driving transistor, and a gate insulating layer interposed between a driving active region of the driving transistor and the driving gate electrode, and between a compensation active region of the compensation transistor and the compensation gate electrode. A dielectric constant in a first portion of the gate insulating layer between the driving active region and the driving gate electrode is greater than a dielectric constant in a second portion of the gate insulating layer between the compensation active region and the compensation gate electrode.

A display device includes a substrate, a semiconductor layer on the substrate, a gate insulating layer on the semiconductor layer, a first upper hydrogen blocking layer on the gate insulating layer and having a positive hydrogen formation energy, a first upper hydrogen capturing layer on the first upper hydrogen blocking layer corresponding to a central portion of the semiconductor layer and having a negative hydrogen formation energy, a gate electrode on the first upper hydrogen capturing layer, a source electrode and a drain electrode connected to both end portions of the semiconductor layer, and a passivation layer on the gate electrode, the source electrode and the drain electrode.

An electrophoresis display with gapped micro partition structure includes a control substrate having a first face and a second face, a driving circuit layer, a control electrode layer, and an electrophoresis layer. The driving circuit layer, the control electrode layer, and the electrophoresis layer are sequentially arranged on the second face. The electrophoresis layer includes a micro partition structure arranged on the control substrate and made from polymer material. The micro partition structure includes a plurality of partition walls to define chambers for accommodating a colloidal solution. Two adjacent partition walls have a gap therebetween and used as yielding space when the electrophoresis display is bent. The area of the gap is not larger than 50% of the area of the partition wall. Or the length of the gap is not longer than 50% of the length of the partition wall.

An electrophoresis display with high aperture ratio includes a control substrate having a first face and a second face, a driving circuit layer, a control electrode layer, an electrophoresis layer, and an opposite substrate. The driving circuit layer includes a plurality of thin film transistors (TFT), a plurality of gate lines, and plurality of data lines. Each of the gate line is connected to the gates of the TFTs and each of the data lines is connected to the sources or the drains of the TFTs. The area of a semiconductor part of the TFT is at least partially overlapped with the area of one of the gate lines or the area of one of the date lines along a projection direction.

A display panel includes a substrate, and an array layer disposed on one side of the substrate. The array layer includes a first-type thin film transistor and a second-type thin film transistor. The first active layer of the first-type thin film transistor and a second active layer of the second-type thin film transistor are both metal oxide active layers, and a sub-threshold swing value of the first-type thin film transistor is greater than a sub-threshold swing value of the second-type thin film transistor.