An electrophoresis display with high aperture ratio includes a control substrate having a first face and a second face, a driving circuit layer, a control electrode layer, an electrophoresis layer, and an opposite substrate. The driving circuit layer includes a plurality of thin film transistors (TFT), a plurality of gate lines, and plurality of data lines. Each of the gate line is connected to the gates of the TFTs and each of the data lines is connected to the sources or the drains of the TFTs. The area of a semiconductor part of the TFT is at least partially overlapped with the area of one of the gate lines or the area of one of the date lines along a projection direction.

An electrophoresis display with gapped micro partition structure includes a control substrate having a first face and a second face, a driving circuit layer, a control electrode layer, and an electrophoresis layer. The driving circuit layer, the control electrode layer, and the electrophoresis layer are sequentially arranged on the second face. The electrophoresis layer includes a micro partition structure arranged on the control substrate and made from polymer material. The micro partition structure includes a plurality of partition walls to define chambers for accommodating a colloidal solution. Two adjacent partition walls have a gap therebetween and used as yielding space when the electrophoresis display is bent. The area of the gap is not larger than 50% of the area of the partition wall. Or the length of the gap is not longer than 50% of the length of the partition wall.

An electrophoresis display with improved micro partition structure includes a control substrate having a first face and a second face, a driving circuit layer, a control electrode layer, and an electrophoresis layer. The driving circuit layer, the control electrode layer, and the electrophoresis layer are sequentially arranged on the second face. The electrophoresis layer includes a micro partition structure arranged on the control substrate and made from polymer material. The micro partition structure includes a plurality of partition walls to define chambers for accommodating a colloidal solution. The height of the partition wall of the micro partition structure is smaller than 25 um.

An electrophoresis display with high aperture ratio includes a control substrate having a first face and a second face, a driving circuit layer, a control electrode layer, an electrophoresis layer, and an opposite substrate. The driving circuit layer includes a plurality of thin film transistors (TFT), a plurality of gate lines, and plurality of data lines. Each of the gate line is connected to the gates of the TFTs and each of the data lines is connected to the sources or the drains of the TFTs. The sum of the data line width and the gate line width is not larger than 10 m. The aperture ratio of the electrophoresis display, viewed from the first face of the control substrate and toward a display area of the electrophoresis display, is not less than 80%.

An electrophoresis display includes a control substrate having a first face and a second face, a driving circuit layer, a control electrode layer, an electrophoresis layer, and an opposite substrate. The viewing face of the electrophoresis display is on the first face of the control substrate. The aperture ratio of the control substrate in the electrophoresis display, viewed from the first face of the control substrate and toward a display area of the electrophoresis display, is not less than 70%.

A substrate assembly includes: a substrate; a first transistor disposed on the substrate, wherein the first transistor includes a first semiconductor layer and the first semiconductor layer is a silicon semiconductor layer; and a second transistor disposed on the substrate, wherein the second transistor includes a second semiconductor layer and a drain electrode electrically connected to the second semiconductor layer, and the second semiconductor layer is an oxide semiconductor layer, wherein the first semiconductor layer of the first transistor is electrically insulated from the drain electrode of the second transistor.

An electronic device includes a substrate, a semiconductor disposed on the substrate, a first signal line, a first electrode disposed on the semiconductor, a first insulating layer disposed on the first electrode, a second electrode disposed on the first insulating layer, a second insulating layer disposed on the second electrode, and a third electrode disposed on the second insulating layer. The first signal line is overlapped with the semiconductor. The first electrode is electrically connected to the semiconductor. The second electrode is electrically connected to the first electrode through a first contact hole of the first insulating layer. The third electrode is electrically connected to the second electrode through a second contact hole of the second insulating layer. The first contact hole and the second contact hole are respectively disposed on two opposite sides of the first signal line in a top view of the electronic device.

A semiconductor device including an oxide semiconductor in which on-state current is high is provided. The semiconductor device includes a first transistor provided in a driver circuit portion and a second transistor provided in a pixel portion; the first transistor and the second transistor have different structures. Furthermore, the first transistor and the second transistor are transistors having a top-gate structure. In an oxide semiconductor film of each of the transistors, an impurity element is contained in regions which do not overlap with a gate electrode. The regions of the oxide semiconductor film which contain the impurity element function as low-resistance regions. Furthermore, the regions of the oxide semiconductor film which contain the impurity element are in contact with a film containing hydrogen. The first transistor provided in the driver circuit portion includes two gate electrodes between which the oxide semiconductor film is provided.

By providing appropriate TFT structures arranged in various circuits of the semiconductor device in response to the functions required by the circuits, it is made possible to improve the operating performances and the reliability of a semiconductor device, reduce power consumption as well as realizing reduced manufacturing cost and increase in yield by lessening the number of processing steps. An LDD region of a TFT is formed to have a concentration gradient of an impurity element for controlling conductivity which becomes higher as the distance from a drain region decreases. In order to form such an LDD region having a concentration gradient of an impurity element, the present invention uses a method in which a gate electrode having a taper portion is provided to thereby dope an ionized impurity element for controlling conductivity accelerated in the electric field so that it penetrates through the gate electrode and a gate insulating film into a semiconductor layer.

An organic light emitting diode display comprises a substrate including a display area in which a pixel is disposed and a peripheral area surrounding the display area, a driving semiconductor layer disposed in the display area on the substrate, a driving gate electrode disposed in the display area on the driving semiconductor layer, a common voltage line disposed in the peripheral area on the substrate and disposed on a same layer as the driving gate electrode, a gate electrode anti-oxidation layer disposed on the driving gate electrode, a common voltage line anti-oxidation layer disposed on the common voltage line, an interlayer insulating layer disposed on the driving semiconductor layer, the driving gate electrode, the common voltage line, the gate electrode anti-oxidation layer, and the common voltage line anti-oxidation layer. A driving source electrode and a driving drain electrode are disposed in the display area on the interlayer insulating layer, and a common voltage applying electrode is disposed in the peripheral area on the interlayer insulating layer and on the same layer as the driving source electrode and the driving drain electrode.