A semiconductor device which includes an oxide semiconductor and in which formation of a parasitic channel due to a gate BT stress is suppressed is provided. Further, a semiconductor device including a transistor having excellent electrical characteristics is provided. The semiconductor device includes a transistor having a dual-gate structure in which an oxide semiconductor film is provided between a first gate electrode and a second gate electrode; gate insulating films are provided between the oxide semiconductor film and the first gate electrode and between the oxide semiconductor film and the second gate electrode; and in the channel width direction of the transistor, the first or second gate electrode faces a side surface of the oxide semiconductor film with the gate insulating film between the oxide semiconductor film and the first or second gate electrode.

A novel display panel that is highly convenient or reliable is provided. A structure in invented which includes a first display element, a first conductive film, a second conductive film, a first insulating film, an intermediate film, a pixel circuit, and a second display element. The first conductive film is electrically connected to the first display element. The second conductive film includes a region overlapping with the first conductive film. The first insulating film includes a region located between the second conductive film and the first conductive film. The first conductive film is located between the second conductive film and part of the intermediate film. The pixel circuit is electrically connected to the second conductive film. The second display element is electrically connected to the pixel circuit. The first insulating film has an opening. The second conductive film is electrically connected to the first conductive film through the opening.

Provided is a novel display panel that is highly convenient or reliable or a display panel with a high pixel aperture ratio. The display panel includes the first display element, the first conductive film electrically connected to the first display element, the second conductive film having a region overlapping with the first conductive film, the second insulating film having a region sandwiched between the second conductive film and the first conductive film, a pixel circuit electrically connected to the second conductive film, and the second display element electrically connected to the pixel circuit. The second insulating film includes an opening, and the second conductive film is electrically connected to the first conductive film in the opening.

A change in electrical characteristics is inhibited and reliability is improved in a semiconductor device using a transistor including an oxide semiconductor. One embodiment of a semiconductor device including a transistor includes a gate electrode, first and second insulating films over the gate electrode, an oxide semiconductor film over the second insulating film, and source and drain electrodes electrically connected to the oxide semiconductor film. A third insulating film is provided over the transistor and a fourth insulating film is provided over the third insulating film. The third insulating film includes oxygen. The fourth insulating film includes nitrogen. The amount of oxygen released from the third insulating film is 110.sup.19/cm.sup.3 or more by thermal desorption spectroscopy, which is estimated as oxygen molecules. The amount of oxygen molecules released from the fourth insulating film is less than 110.sup.19/cm.sup.3.

A semiconductor device (100) includes: a substrate (11); a first thin film transistor (10A) supported on the substrate (11), the first thin film transistor (10A) having a first active region (13c) which mainly contains a crystalline silicon; and a second thin film transistor (10B) being supported on the substrate (11), the second thin film transistor (10B) having a second active region (17c) which mainly contains an oxide semiconductor having a crystalline portion.

A display panel includes a base substrate, a third transistor and a fourth transistor. The third transistor and the fourth transistor are formed on the base substrate. The third transistor includes a sixth gate electrode, a third active layer, a third source electrode, and a third drain electrode. The third active layer includes an oxide semiconductor. The fourth transistor includes an eighth gate electrode, a fourth active layer, a fourth source electrode, and a fourth drain electrode. The fourth active layer includes another oxide semiconductor. Along a direction perpendicular to the base substrate, a distance between the sixth gate electrode and the third active layer is D6. A channel region of the third transistor defined by the sixth gate electrode is a sixth channel region. A length of the sixth channel region is L6. A sixth area S6=L6D6.

A display panel includes a base substrate, a first transistor and a second transistor. The first transistor and the second transistor are formed on the base substrate. The first transistor includes a first active layer, a first gate electrode, a first source electrode, and a first drain electrode. The first active layer includes silicon. The second transistor includes a second active layer, a second gate electrode, a second source electrode, and a second drain electrode. The second active layer includes an oxide semiconductor. A length of a channel region of the first transistor is L1. Along a direction perpendicular to the base substrate, a distance between the first gate electrode and the first active layer is D1. The first transistor further includes a third gate electrode. Along the direction perpendicular to the base substrate, a distance between the third gate electrode and the first active layer is D3, and D1<D3.

A display device is described that has reduced resistance in one or more of the gate, common, data electrical lines that control the operation of the pixels of the display device. Reduced resistance is achieved by forming additional metal and/or metal-alloy layers on the gate, common, and/or data lines in such a manner so that the cross-sectional area of those lines is increased. As a consequence, each such line is formed so as to be thicker than could otherwise be achieving without causing defects in the rubbing process of an alignment layer. Additionally, no widening of these lines is needed, thus preserving the aspect ratio of the device. The gate insulating and semiconducting layers that in part make up the thin film transistors that help control the operation of the pixels of the device may also be designed to take into account the increased thickness of the lines.

A thin film transistor (TFT) array substrate is provided that includes a TFT on a substrate. The TFT can include an active layer, gate electrode, source electrode, drain electrode, first insulating layer between the active layer and the gate electrode, and second insulating layer between the gate electrode and the source and drain electrodes. A pixel electrode is disposed on the first and second insulating layers. A capacitor including a lower electrode is disposed on a same layer as the gate electrode and an upper electrode. A third insulating layer directly between the second insulating layer and the pixel electrode and between the lower electrode and the upper electrode. A fourth insulating layer covers the source electrode, the drain electrode, and the upper electrode, and exposes the pixel electrode and can further expose a pad electrode.

A semiconductor device, a method for manufacturing the same, and an electronic device including the same are provided. The semiconductor device includes a first transistor and a second transistor. The first transistor includes a first channel layer and a first ion gel. The second transistor includes a second channel layer and a second ion gel. The first channel layer and the second channel layer may include, for example, graphene. The first ion gel and the second ion gel include different ionic liquids. The first ion gel and the second ion gel include different cations and/or different anions. One of the first transistor and the second transistor is a p-type transistor, and the other one is an n-type transistor. The combination of the first transistor and the second transistor constitutes an inverter.