A semiconductor device includes a first transistor including a first electrode, a first insulating layer above the first electrode, the first insulating layer having a first side wall, a first oxide semiconductor layer on the first side wall, the first oxide semiconductor layer being connected with the first electrode, a first gate electrode, a first gate insulating layer, and a second electrode above the first insulating layer, the second electrode being connected with the first oxide semiconductor layer; and a second transistor including a third electrode, a fourth electrode separated from the third electrode, a second oxide semiconductor layer between the third electrode and the fourth electrode, the second oxide semiconductor layer being connected with each of the third electrode and the fourth electrode, a second gate electrode, and a second gate insulating layer.

A semiconductor device including a circuit which does not easily deteriorate is provided. The semiconductor device includes a first transistor, a second transistor, a first switch, a second switch, and a third switch. A first terminal of the first transistor is connected to a first wiring. A second terminal of the first transistor is connected to a second wiring. A gate and a first terminal of the second transistor are connected to the first wiring. A second terminal of the second transistor is connected to a gate of the first transistor. The first switch is connected between the second wiring and a third wiring. The second switch is connected between the second wiring and the third wiring. The third switch is connected between the gate of the first transistor and the third wiring.

A semiconductor device including an oxide semiconductor in which on-state current is high is provided. The semiconductor device includes a first transistor provided in a driver circuit portion and a second transistor provided in a pixel portion; the first transistor and the second transistor have different structures. Furthermore, the first transistor and the second transistor are transistors having a top-gate structure. In an oxide semiconductor film of each of the transistors, an impurity element is contained in regions which do not overlap with a gate electrode. The regions of the oxide semiconductor film which contain the impurity element function as low-resistance regions. Furthermore, the regions of the oxide semiconductor film which contain the impurity element are in contact with a film containing hydrogen. The first transistor provided in the driver circuit portion includes two gate electrodes between which the oxide semiconductor film is provided.

In the case where a material containing an alkaline-earth metal in a cathode, is used, there is a fear of the diffusion of an impurity ion (such as alkaline-earth metal ion) from the EL element to the TFT being generated and causing the variation of characteristics of the TFT. Therefore, as the insulating film provided between TFT and EL element, a film containing a material for not only blocking the diffusion of an impurity ion such as an alkaline-earth metal ion but also aggressively absorbing an impurity ion such as an alkaline-earth metal ion is used.

Systems, methods, and apparatus for an improved body tie construction that produces all the benefits of conventional body tie (H-gate, T-gate), without the limitations and degradations associated with those constructions are described. The improved body tie construction is configured to have a lower resistance body tie when the transistor is off (Vg approximately 0 volts). When the transistor is on (Vg>Vt), the resistance to the body tie is much higher, reducing the loss of performance associated with presence of body tie.

A semiconductor device including a circuit which does not easily deteriorate is provided. The semiconductor device includes a first transistor, a second transistor, a first switch, a second switch, and a third switch. A first terminal of the first transistor is connected to a first wiring. A second terminal of the first transistor is connected to a second wiring. A gate and a first terminal of the second transistor are connected to the first wiring. A second terminal of the second transistor is connected to a gate of the first transistor. The first switch is connected between the second wiring and a third wiring. The second switch is connected between the second wiring and the third wiring. The third switch is connected between the gate of the first transistor and the third wiring.

Decrease of the output voltage of the logic circuit is inhibited by raising the gate voltage using a capacitor. In a first transistor, a drain and a gate are electrically connected to a first wiring, and a source is electrically connected to a first node. In a second transistor, a drain is electrically connected to the first node, a source is electrically connected to a second wiring, and a gate is electrically connected to a second node. In a third transistor, a drain is electrically connected to a third wiring, and a source is electrically connected to a third node, and a gate is electrically connected to the first node. In a fourth transistor, a drain is electrically connected to the third node, a source is electrically connected to a fourth wiring, and a gate is electrically connected to the second node. In a capacitor, one electrode is electrically connected to the first node, and the other electrode is electrically connected to the third node. OS transistors are preferably used as the transistors above.

A display device includes: a plurality of pixels connected to gate lines and data lines; a gate driver to supply a gate signal to the gate lines; and a data driver to supply a data signal to the data lines. The gate driver includes: a first transistor including a first active layer at a first layer; and a second transistor including a second active layer at a second layer on the first layer.

A novel display apparatus is provided. The display apparatus includes a first layer including a plurality of pixel circuits, a second layer provided over the first layer, a plurality of optical lenses provided over the second layer, a display region, and a plurality of light-receiving regions. The display region includes a first pixel circuit provided in the first layer and a light-emitting device provided in the second layer. The light-receiving region includes a second pixel circuit provided in the first layer and a light-receiving device provided in the second layer. The plurality of light-receiving regions are provided around the display region. The optical lens is provided at a position overlapping with the light-receiving region.

An array substrate and a manufacturing method thereof are provided. The array substrate includes a substrate, an active layer, a first insulating layer, a first metal layer, a second insulating layer, and a second metal layer. The array substrate includes a thin film transistor (TFT) area, and the second metal layer includes a source-drain metal sub-layer located in the TFT area. The TFT area is defined with an active layer exposed area. The array substrate includes a barrier layer, and an orthographic projection of the barrier layer on the active layer at least partially covers an orthographic projection of the active layer exposed area on the active layer.