An integrated circuit structure includes a first vertical transistor and a second vertical transistor. The first vertical transistor includes a first semiconductor channel, a first top source/drain region over the first semiconductor channel, and a first top source/drain pad overlapping the first top source/drain region. The second vertical transistor includes a second semiconductor channel, a second top source/drain region over the second semiconductor channel, and a second top source/drain pad overlapping the second top source/drain region. A local interconnector interconnects the first top source/drain pad and the second top source/drain pad. The first top source/drain pad, the second top source/drain pad, and the local interconnector are portions of a continuous region, with no distinguishable interfaces between the first top source/drain pad, the second top source/drain pad, and the local interconnector.

A method for forming a nanowire device comprises forming a fin on a substrate, depositing a first layer of insulator material on the substrate, etching to remove portions of the first layer of insulator material to reduce a thickness of the first layer of insulator material, epitaxially growing a first layer of semiconductor material on exposed sidewall portions of the fin, depositing a second layer of insulator material on the first layer of insulator material, etching to remove portions of the second layer of insulator material to reduce a thickness of the second layer of insulator material, and etching to remove portions of the first layer of semiconductor material to expose portions of the fin and form a first nanowire and a second nanowire.

The generation of a variation in properties of vertical transistors is restrained. A vertical MOS transistor is formed in a semiconductor substrate. A first interlayer dielectric film and a first source wiring are formed over the front surface of the substrate. The first source wiring is formed over the first interlayer dielectric film, and is overlapped with the vertical MOS transistor as viewed in plan. Contacts are buried in the first interlayer dielectric film. Through the contacts, an n-type source layer of vertical MOS transistor is coupled with the first source wiring. Openings are made in the first source wiring.

A semiconductor device including a substrate, a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, and a gate stack surrounding a periphery of the channel layer. The channel layer includes a semiconductor material causing an increased ON current and/or a reduced OFF current as compared to Si.

A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.

A semiconductor device including a semiconductor substrate; a trench formed in a front surface of the semiconductor substrate; a gate conducting portion formed within the gate trench; and a first region formed adjacent to the trench in the front surface of the semiconductor substrate and having a higher impurity concentration than the semiconductor substrate. A shoulder portion is provided on a side wall of the gate trench between the top end of the gate conducting portion and the front surface of the semiconductor substrate and has an average slope, relative to a depth direction of the semiconductor substrate, that is greater than a slope of the side wall of the gate trench at a position opposite the top end of the gate conducting portion, and a portion of the first region that contacts the gate trench is formed as a deepest portion thereof.

A vertical field effect device includes a substrate and a vertical channel including In.sub.xGa.sub.1-xAs on the substrate. The vertical channel includes a pillar that extends from the substrate and includes opposing vertical surfaces. The device further includes a stressor layer on the opposing vertical surfaces of the vertical channel. The stressor layer includes a layer of epitaxial crystalline material that is epitaxially formed on the vertical channel and that has lattice constant in a vertical plane corresponding to one of the opposing vertical surfaces of the vertical channel that is greater than a corresponding lattice constant of the vertical channel.

A semiconductor device comprises a set of selection transistors, such as in a three-dimensional memory structure or stack having resistance change memory cells arranged along vertical bit lines. Each selection transistor has a non-shared control gate and a shared control gate. The transistor bodies may have an unequal pitch and a common height. Some of the transistor bodies can be misaligned with the vertical bit lines to fit the transistors to the stack. A method for programming the three-dimensional memory structure includes forming one or two channels in a transistor body to provide a current to selected memory cells. Programming can initially use one channel and subsequently use two channels based on a programming progress. A method for fabricating a semiconductor device includes etching a gate conductor material so that shared and non-shared control gates have a common height.

A channel fin extends vertically above a bottom source/drain region, a protective liner is positioned along opposite sidewalls of the bottom source/drain region. The bottom source/drain region is positioned above a semiconductor layer in contact with a first portion of an inner spacer. A first metal layer is positioned between the first portion of the inner spacer and a second portion of the inner spacer, the first portion of the inner spacer partially covers a top surface of the first metal layer and the second portion of the inner spacer substantially covers a bottom surface of the first metal layer for providing a buried power rail. A shallow trench isolation region is positioned above an exposed portion of the first metal layer, the shallow trench isolation region is adjacent to the first portion of the inner spacer, the semiconductor layer, and the bottom source/drain region.

An all-oxide transistor structure includes a substrate having an upper surface and a first transistor disposed on the upper surface of the substrate. The first transistor includes a first drain, a first dielectric layer, a first source, at least one first opening and a first channel layer. The first drain, the first dielectric layer and the first source are disposed on the substrate along a first direction, and the first direction is parallel to a normal direction of the upper surface. The first opening passes through the first drain, the first dielectric layer and the first source along the first direction. The first channel layer, the first gate dielectric layer and the first gate are disposed in the first opening. The first gate dielectric layer is disposed on the first channel layer. The first gate is disposed on the first gate dielectric layer.