The present disclosure discloses a semiconductor device, a method of manufacturing the same, and a semiconductor package structure. The semiconductor device including a substrate, a multilayer semiconductor layer located on one side of the substrate, in which a Two-Dimensional Electron Gas is formed, a first source, a first gate and a first drain located on one side of the multilayer semiconductor layer and located within an active region of the multilayer semiconductor layer, the first gate being located between the first source and the first drain, and a back surface gate contact electrode located on one side of the substrate away from the multilayer semiconductor layer, wherein the first gate is electrically connected to the back surface gate contact electrode. A signal is provided from the back surface of the semiconductor device to the first gate, to reduce the parasitic inductance and parasitic resistance caused by the device during the packaging process.

An integrated circuit includes a set of power rails, a set of active regions, a first set of conductive lines and a first and a second set of vias. The set of power rails is configured to supply a first or second supply voltage, and is on a first level of a back-side of a substrate. The set of active regions is a second level of a front-side of the substrate. The first set of conductive lines extend in a second direction and overlap the set of active regions. The first set of vias is between and electrically couples the set of active regions and the first set of conductive lines together. The second set of vias is between and electrically couples the first set of conductive lines and the set of power rails together.

The present disclosure describes a semiconductor device that includes a transistor. The transistor includes a source/drain region that includes a front surface and a back surface opposite to the front surface. The transistor includes a salicide region on the back surface and a channel region in contact with the source/drain region. The channel region has a front surface co-planar with the front surface of the source/drain region. The transistor further includes a gate structure disposed on a front surface of the channel region. The semiconductor device also includes a backside contact structure that includes a conductive contact in contact with the salicide region and a liner layer surrounding the conductive contact.

Gate-all-around integrated circuit structures having differential nanowire thickness and gate oxide thickness, and methods of fabricating gate-all-around integrated circuit structures having differential nanowire thickness and gate oxide thickness, are described. For example, an integrated circuit structure includes a nanowire with an outer thickness and an inner thickness, the inner thickness less than the outer thickness. The nanowire tapers from outer regions having the outer thickness to an inner region having the inner thickness. A dielectric material is on and surrounding the nanowire such that a combined thickness of the nanowire and the dielectric material in the inner region is approximately the same as the outer thickness of the nanowire.

Device structures and methods for reducing current collapse in high electron mobility transistors (HEMT) using aluminum nitride back barrier and in-situ two-step passivation are disclosed. In one aspect, the HEMT includes a back barrier layer including Al and N on a substrate, a channel layer including Ga and N on the back barrier layer, an Al.sub.xGa.sub.1-xN layer on the channel layer, a first passivation layer on the Al.sub.xGa.sub.1-xN layer, source and drain ohmic contacts, a T-shaped gate electrode at a location on a surface between the drain ohmic contact and the source ohmic contact, and a second passivation layer on the first passivation layer covering the surface and the T-shaped gate electrode.

A semiconductor device includes a substrate having a main surface and a back surface opposite to the main surface, a first transistor disposed on the main surface, a second transistor disposed on the main surface, a third transistor disposed on the main surface between the first transistor and the second transistor, a first gate line disposed on the main surface, and a back-surface metal layer disposed on the back surface.

A semiconductor device includes a substrate having a main surface and a back surface, and first and second transistors. A first gate wiring is provided on the main surface a disposed in a first source electrode of the first transistor when viewed from a direction, and is electrically connected to a first gate electrode thereof. The second source electrode is interposed between a second gate electrode of the second transistor and a first gate wiring. A back metal layer is provided on the back surface and is electrically connected to the first source electrode and a second source electrode of the second transistor through a first via hole and a second via hole which overlap the first source electrode and the second source electrode, respectively, when viewed in a thickness direction of the substrate.

An integrated circuit (IC) structure includes a gate structure, a source epitaxial structure, a drain epitaxial structure, a front-side interconnection structure, a backside dielectric layer, an epitaxial regrowth layer, and a backside via. The source epitaxial structure and the drain epitaxial structure are respectively on opposite sides of the gate structure. The front-side interconnection structure is over a front-side of the source epitaxial structure and a front-side of the drain epitaxial structure. The backside dielectric layer is over a backside of the source epitaxial structure and a backside of the drain epitaxial structure. The epitaxial regrowth layer is on the backside of a first one of the source epitaxial structure and the drain epitaxial structure. The backside via extends through the backside dielectric layer and overlaps the epitaxial regrowth layer.

The present disclosure relates to an integrated chip including a semiconductor structure including a gate, a first source/drain region, and a second source/drain region. A power rail is disposed under the gate, the first source/drain region, and the second source/drain region. The power rail is in electrical connection with the first source/drain region.

A semiconductor device includes a first source/drain region connected to a back end of line (BEOL) through a first contact and a first via, and a second source/drain region connected to the BEOL through a second contact, a lateral contact, and a second via. The first via passes through the lateral contact.