A semiconductor device includes a transistor. The transistor includes a source region and a drain region disposed adjacent to a first main surface of a semiconductor substrate, a first gate electrode and a second gate electrode, the first gate electrode being disconnected from the second gate electrode. The transistor further includes a body region. The first gate electrode is adjacent to a first portion of the body region and the second gate electrode is adjacent to a second portion of the body region. The transistor further includes first trenches patterning the first portion of the body region into a first ridge, and second trenches patterning the second portion of the body region into a second ridge. The first gate electrode is arranged in at least one of first trenches, and the second gate electrode is arranged in at least one of the second trenches.

A semiconductor device includes a semiconductor substrate having a first conductivity type. A gate structure is supported by a surface of the semiconductor substrate, and a current carrying region (e.g., a drain region of an LDMOS transistor) is disposed in the semiconductor substrate at the surface. The device further includes a drift region of a second, opposite conductivity type disposed in the semiconductor substrate at the surface. The drift region extends laterally from the current carrying region to the gate structure. The device further includes a buried region of the second conductivity type disposed in the semiconductor substrate below the current carrying region. The buried region is vertically aligned with the current carrying region, and a portion of the semiconductor substrate with the first conductivity type is present between the buried region and the current carrying region.

A semiconductor device with a substrate, a low defect layer formed in a fixed position relative to the substrate, and a barrier layer comprising III-N semiconductor material formed on the low-defect layer and forming an electron gas in the low-defect layer. The device also has a source contact, a drain contact, and a gate contact for receiving a potential, the potential for adjusting a conductive path in the electron gas and between the source contact and the drain contact. Lastly, the device has a one-sided PN junction between the barrier layer and the substrate.

A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench contacts over and abutting an interfacial layer portion of at least one of the source region and the drain region; wherein the interfacial layer includes boron in an amount in a range from about 510.sup.21 to about 510.sup.22 atoms/cm.sup.2.

A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench contacts over and abutting an interfacial layer portion of at least one of the source region and the drain region; wherein the interfacial layer includes boron in an amount in a range from about 510.sup.21 to about 510.sup.22 atoms/cm.sup.2.

In accordance with an embodiment, a semiconductor component includes a plurality of layers of compound semiconductor material over a body of semiconductor material and first and second filled trenches extending into the plurality of layers of compound semiconductor material. The first trench has first and second sidewalls and a floor and a first dielectric liner over the first and second sidewalls and the second trench has first and second sidewalls and a floor and second dielectric liner over the first and second sidewalls of the second trench.

A lateral superjunction MOSFET device includes a gate structure and a first column connected to the lateral superjunction structure. The lateral superjunction MOSFET device includes the first column to receive current from the channel when the MOSFET is turned on and to distribute the channel current to the lateral superjunction structure functioning as the drain drift region. In some embodiment, the MOSFET device includes a second column disposed in close proximity to the first column. The second column disposed near the first column is used to pinch off the first column when the MOSFET device is to be turned off and to block the high voltage being sustained by the MOSFET device at the drain terminal from reaching the gate structure. In some embodiments, the lateral superjunction MOSFET device further includes termination structures for the drain, source and body contact doped region fingers.

A dual channel trench LDMOS transistor includes a semiconductor layer of a first conductivity type formed on a substrate; a first trench formed in the semiconductor layer where a trench gate is formed in an upper portion of the first trench; a body region of the second conductivity type formed in the semiconductor layer adjacent the first trench; a source region of the first conductivity type formed in the body region and adjacent the first trench; a planar gate overlying the body region; a drain drift region of the first conductivity type formed in the semiconductor layer and in electrical contact with a drain electrode; and alternating N-type and P-type regions formed in the drain drift region with higher doping concentration than the drain-drift regions to form a super-junction structure in the drain drift region.

A laterally diffused metal oxide semiconductor (LDMOS) transistor structure with improved unclamped inductive switching immunity. The LDMOS includes a substrate and an adjacent epitaxial layer both of a first conductivity type. A gate structure is above the epitaxial layer. A drain region and a source region, both of a second conductivity type, are within the epitaxial layer. A channel is formed between the source and drain region and arranged below the gate structure. A body structure of the first conductivity type is at least partially formed under the gate structure and extends laterally under the source region, wherein the epitaxial layer is less doped than the body structure. A conductive trench-like feed-through element passes through the epitaxial layer and contacts the substrate and the source region. The LDMOS includes a tub region of the first conductivity type formed under the source region, and adjacent laterally to and in contact with said body structure and said trench-like feed-through element.

Methods of forming semiconductor devices include epitaxially growing a III-V base layer over a first substrate in a first deposition chamber. The III-V base layer is transferred from the first substrate to a second substrate, and at least one III-V device layer is epitaxially grown on the III-V base layer in a second deposition chamber separate from the first deposition chamber while the III-V base layer is disposed on the second substrate. The first substrate exhibits an average coefficient of thermal expansion (CTE) closer to an average CTE exhibited by the III-V base layer than an average CTE exhibited by the second substrate. Semiconductor devices may be fabricated using such methods.