Disclosed is a semiconductor device comprising a thin film transistor and wirings connected to the thin film transistor, in which the thin film transistor has a channel formation region in an oxide semiconductor layer, and a copper metal is used for at least one of a gate electrode, a source electrode, a drain electrode, a gate wiring, a source wiring, and a drain wiring. The extremely low off current of the transistor with the oxide semiconductor layer contributes to reduction in power consumption of the semiconductor device. Additionally, the use of the copper metal allows the combination of the semiconductor device with a display element to provide a display device with high display quality and negligible defects, which results from the low electrical resistance of the wirings and electrodes formed with the copper metal.

In an embodiment a method for manufacturing a plurality of semiconductor chips includes providing an epitaxial semiconductor layer sequence having a plurality of epitaxial semiconductor layer stacks, the epitaxial semiconductor layer stacks having active regions configured for generating electromagnetic radiation, applying a plurality of logical chips on or over the epitaxial semiconductor layer sequence, the logical chips including at least one integrated circuit configured for controlling the active regions, wherein the logical chips are at least partially provided separately from each other, and wherein the logical chips are CMOS chips, the CMOS chips including at least one p-channel MOSFET and at least one n-channel MOSFET being part of the at least one integrated circuit, and embedding the plurality of logical chips in a mold compound.

Various embodiments of solid state transducer (SST) devices are disclosed. In several embodiments, a light emitter device includes a metal-oxide-semiconductor (MOS) capacitor, an active region operably coupled to the MOS capacitor, and a bulk semiconductor material operably coupled to the active region. The active region can include at least one quantum well configured to store first charge carriers under a first bias. The bulk semiconductor material is arranged to provide second charge carriers to the active region under the second bias such that the active region emits UV light.

A vertical solid state device comprising: a connection pad; and side walls comprising a metal-insulator-semiconductor (MIS) structure; wherein a gate of the MIS structure is shorted to at least one contact of the vertical solid state device and a threshold voltage (VT) of the MIS structure is adjusted to increase the efficiency of the device.

In an embodiment a radiation-emitting semiconductor component includes a carrier having a first main surface and at least one lateral surface extending transversely to the first main surface, at least one semiconductor chip arranged on the first main surface of the carrier and configured to emit radiation at a radiation emission face and a housing molded onto the carrier and the at least one semiconductor chip, wherein the at least one lateral surface of the carrier is uncovered by the housing, wherein the housing comprises a depression arranged on the radiation emission face of the at least one semiconductor chip, wherein the housing is laterally delimited by at least one housing wall, and wherein the at least one housing wall is laterally offset in a direction toward the depression with respect to an edge of the carrier delimiting the first main surface.

An LED (e.g., a UV-LED) structure includes a substrate, a first cathode layer, a second cathode layer, a light emitting layer, an anode layer, an anode contact, and a cathode contact. The first cathode layer has a first aluminum composition. The second cathode layer is disposed on top of the first cathode layer and has a second aluminum composition greater than the first aluminum composition. A two-dimensional electron gas (2DEG) layer is formed at an interface between the first cathode layer and the second cathode layer during operation of the LED structure.

An optoelectronic device comprises a gapped graphene system (GGS) a top gate electrode, a bottom gate electrode and a controller configured for applying a voltage bias between the gate electrodes to effect a bandgap in the GGS, wherein the bandgap is selected to allow the GGS to receive or emit light having a terahertz frequency.

Provided are a semiconductor light source and a driver circuit thereof. The semiconductor light source includes an active layer, a first semiconductor layer, a second semiconductor layer, a first electrode, a second electrode, and a third electrode. The first semiconductor layer and the second semiconductor layer are located on two opposite sides of the active layer. The first electrode is in ohmic contact with the first semiconductor layer. The third electrode is in ohmic contact with the second semiconductor layer. A first dielectric layer is disposed between the first electrode and the second electrode. The first semiconductor layer is a p-type semiconductor layer, and the second semiconductor layer is an n-type semiconductor layer. Alternatively, the first semiconductor layer is an n-type semiconductor layer, and the second semiconductor layer is a p-type semiconductor layer.

The present disclosure relates to a solid state micro device structure that has a microdevice formed on a substrate, with p and n doped layers, active layers between at least the two doped layers, pads coupled to each doped layer, and wherein the n-doped layer is modulated to have a lower conductivity towards an edge of the device. The invention further involves, dielectric layer, conductive layer, passivation layer and MIS structure.