A wide-band-gap diode and manufacturing method thereof are provided. The method of manufacturing a wide-band-gap diode involves growing an N-type doped epitaxial layer on an N-doped substrate. P-type ions are implanted into the epitaxial layer to form an active area, a junction termination extension region, and an edge region. The active area exhibits an axially symmetric graticule pattern, with higher doping area density towards the center of the active area. The junction termination extension region surrounds the active area, and the edge region encircles both of the active area and the junction termination extension region to enhance the wide-band-gap diode's capability to withstand surge currents.

A semiconductor device includes a semiconductor substrate and a p-doped layer formed on the substrate having a dislocation density exceeding 10.sup.8 cm.sup.2. An n-type layer is formed on or in the p-doped layer. The n-type layer includes a II-VI material configured to tolerate the dislocation density to form an electronic device with reduced leakage current over a device with a III-V n-type layer.

A method for transferring an assembly of oriented nanowires from a liquid interface onto a surface including providing a first liquid and a second liquid, wherein the first and second liquids phase separate into a bottom phase, a top phase and an interface between the bottom phase and the top phase, providing nanowires in the first and second liquids such that the majority of the nanowires are located at the interface and providing the nanowires onto a substrate such that a majority of the nanowires are aligned with respect to each other on the substrate.

An electronic device includes a substrate and at least two electrodes spaced by a nanogap, wherein the at least two electrodes are bridged by at least one nanoparticle and wherein the at least one nanoparticle has an overlap area with the at least two electrodes higher than 2% of the area of the at least one nanoparticle. A method of manufacturing the electronic device and the use of the electronic device in photodetector, transistor, phototransistor, optical modulator, electrical diode, photovoltaic cell or electroluminescent component are also described.

A thin film transistor, a manufacturing method thereof, and a display device are provided. The thin film transistor includes a gate electrode (21), an active layer (23), a source electrode (241) and a drain electrode (242). The source electrode (241) and the drain electrode (242) are formed of at least two materials, the forming materials of the source electrode (241) and the drain electrode (242) can create a cell reaction in a corresponding etching solution so as to be etched, and material of the active layer (23) is not corroded by the etching solution. With the thin film transistor and manufacturing method thereof according to embodiments of the invention, a problem that an active layer is liable to be corroded in an etching procedure of a source electrode and a drain electrode can be solved, and thus the thin film transistor device can be manufactured by using a back channel etch process. Consequently, the process number for manufacture of the thin film transistor is decreased, and the manufacturing cost is saved.

A semiconductor device includes a monocrystalline substrate configured to form a channel region between two recesses in the substrate. A gate conductor is formed on a passivation layer over the channel region. Dielectric pads are formed in a bottom of the recesses and configured to prevent leakage to the substrate. Source and drain regions are formed in the recesses on the dielectric pads from a deposited non-crystalline n-type material with the source and drain regions making contact with the channel region.

A semiconductor device includes a monocrystalline substrate configured to form a channel region between two recesses in the substrate. A gate conductor is formed on a passivation layer over the channel region. Dielectric pads are formed in a bottom of the recesses and configured to prevent leakage to the substrate. Source and drain regions are formed in the recesses on the dielectric pads from a deposited non-crystalline n-type material with the source and drain regions making contact with the channel region.

A pixel structure and a method of manufacturing a pixel structure are provided. The pixel structure includes an active device, a gate insulation layer, a dielectric insulation layer, a capacitance electrode, a protection layer and a pixel electrode. The active device includes a gate, a semiconductor channel layer, a source and a drain. The dielectric insulation layer covers the semiconductor channel layer. A dielectric index of the dielectric insulation layer is greater than a dielectric index of the gate insulation layer. The capacitance electrode is overlapped with the drain. The capacitance electrode, the drain and the dielectric insulation layer between the two constitute a storage capacitor structure. The protection layer is disposed on the dielectric insulation layer and the capacitance electrode is located between the protection layer and the dielectric insulation layer. The pixel electrode is disposed on the protection layer and connected to the drain of the active device.

There is provided an oxide sintered body including indium, tungsten and zinc, wherein the oxide sintered body includes a bixbite type crystal phase as a main component and has an apparent density of higher than 6.5 g/cm.sup.3 and equal to or lower than 7.1 g/cm.sup.3, a content rate of tungsten to a total of indium, tungsten and zinc is higher than 1.2 atomic % and lower than 30 atomic %, and a content rate of zinc to the total of indium, tungsten and zinc is higher than 1.2 atomic % and lower than 30 atomic %. There are also provided a sputtering target including this oxide sintered body, and a semiconductor device including an oxide semiconductor film formed by a sputtering method by using the sputtering target.

In one example, a method for fabricating a semiconductor device includes etching a layer of silicon to form a plurality of fins and growing layers of a semiconductor material directly on sidewalls of the plurality of fins, wherein the semiconductor material and surfaces of the sidewalls have different crystalline properties.