A thin film transistor includes an active layer of an oxide semiconductor, a gate electrode provided on or under the active layer while being spaced apart from the active layer and overlapping with at least a portion of the active layer, and a gate insulating film between the active layer and the gate electrode, wherein the active layer includes copper (Cu).

The disclosure relates to a simulation method for selecting an optimal composition ratio of an oxide semiconductor. The oxide semiconductor includes at least two elements selected from the group consisting of indium (In), gallium (Ga), zinc (Zn), tin (Sn), silver (Ag), aluminum (Al), cadmium (Cd), magnesium (Mg), antimony (Sb), silicon (Si), titanium (Ti), and zirconium (Zr); oxygen (O); and inevitable impurities. The simulation method includes setting a simulation target composition ratio set including various composition ratios of elements constituting the oxide semiconductor, checking whether the oxide semiconductor satisfies Formulas 1, 2, and 3 for each of the various composition ratios included in the simulation target composition ratio set, and selecting a composition ratio satisfying Formulas 1, 2, and 3 as an optimal composition ratio. Formulas 1, 2, and 3 may be the same as described in the specification.

Provided are a junction barrier Schottky diode having a trench structure that has high surge resistance and reduced energy loss during switching operation, and a method for manufacturing the same. An embodiment provides a junction barrier Schottky diode 1 comprising: an n-type semiconductor layer 11 having a plurality of trenches 111; a p-type semiconductor film 12 provided in contact with an inner surface of the a plurality of trenches 111; an anode electrode 13 which is provided on a first surface 113 of the n-type semiconductor layer 11 and in contact with a mesa-shaped portion 112 of the n-type semiconductor layer 11, a part of the anode electrode 13 being covered by the p-type semiconductor film 12 in the plurality of trenches 111; and a cathode electrode 14 provided on a second surface 114 of the n-type semiconductor layer 11 directly or with another layer therebetween.

Provided are a junction barrier Schottky diode having a trench structure that has high surge resistance and reduced energy loss during switching operation, and a method for manufacturing the same. An embodiment provides a junction barrier Schottky diode 1 comprising: an n-type semiconductor layer 11 having a plurality of trenches 111; a p-type semiconductor film 12 provided in contact with an inner surface of the a plurality of trenches 111; an anode electrode 13 which is provided on a first surface 113 of the n-type semiconductor layer 11 and in contact with a mesa-shaped portion 112 of the n-type semiconductor layer 11, a part of the anode electrode 13 being covered by the p-type semiconductor film 12 in the plurality of trenches 111; and a cathode electrode 14 provided on a second surface 114 of the n-type semiconductor layer 11 directly or with another layer therebetween.

A novel material and a transistor including the novel material are provided. One embodiment of the present invention is a composite oxide including at least two regions. One of the regions includes In, Zn and an element M1 (the element M1 is one or more of Al, Ga, Si, B, Y, Ti, Fe, Ni, Ge, Zr, Mo, La, Ce, Nd, Hf, Ta, W, Mg, V, Be, and Cu) and the other of the regions includes In, Zn, and an element M2 (the element M2 is one or more of Al, Ga, Si, B, Y, Ti, Fe, Ni, Ge, Zr, Mo, La, Ce, Nd, Hf, Ta, W, Mg, V, Be, and Cu). In an analysis of the composite oxide by energy dispersive X-ray spectroscopy, the detected concentration of the element M1 in a first region is less than the detected concentration of the element M2 in a second region, and a surrounding portion of the first region is unclear in an observed mapping image of the energy dispersive X-ray spectroscopy.

The functional photoresist for patterning a nanoparticle thin film including nanoparticles on a substate includes: a photoactive compound (PAC); and a functional ligand that is bound to surfaces of the nanoparticles and controls physical properties of the nanoparticles.

Disclosed herein are transistor electrode-channel arrangements, and related methods and devices. For example, in some embodiments, a transistor electrode-channel arrangement may include a channel material, source/drain electrodes provided over the channel material, and a sealant at least partially enclosing one or more of the source/drain electrodes, wherein the sealant includes one or more metallic conductive materials.

Disclosed herein are transistor electrode-channel arrangements, and related methods and devices. For example, in some embodiments, a transistor electrode-channel arrangement may include a channel material, source/drain electrodes provided over the channel material, and a sealant at least partially enclosing one or more of the source/drain electrodes, wherein the sealant includes one or more metallic conductive materials.

A method for manufacturing an integrated circuit device is provided. The method includes depositing a dielectric layer over a substrate; depositing a first gate electrode layer over the dielectric layer; removing a first portion of the dielectric layer to leave an opening between the first gate electrode layer, the substrate, and second portions of the dielectric layer; depositing a first gate dielectric layer, such that the first gate dielectric layer has a first portion in the opening and a second portion over a top surface of the first gate electrode layer; and depositing a semiconductor layer, such that the semiconductor layer has a first portion in the opening and a second portion over a top surface of the first gate dielectric layer.

A semiconductor device includes a substrate including a fin-shaped active region that protrudes from the substrate, a gate insulating film covering a top surface and both side walls of the fin-shaped active region, a gate electrode on the top surface and the both side walls of the fin-shaped active region and covering the gate insulating film, one pair of insulating spacers on both side walls of the gate electrode, one pair of source/drain region on the fin-shaped active region and located on both sides of the gate electrode, and a lower buffer layer between the fin-shaped active region the source/drain region. The source/drain regions include a compound semiconductor material including atoms from different groups. The lower buffer layer includes a compound semiconductor material that is amorphous and includes atoms from different groups.